bec78e32d6
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef DEVICE_DRAM_COMMON_H
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#define DEVICE_DRAM_COMMON_H
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#include <console/console.h>
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#include <stdint.h>
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/**
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* \brief Convenience definitions for TCK values
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*
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* Different values for tCK, representing standard DDR3 frequencies.
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* These values are in 1/256 ns units.
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* @{
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*/
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#define NS2MHZ_DIV256 (1000 << 8)
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#define TCK_1333MHZ 192
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#define TCK_1200MHZ 212
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#define TCK_1100MHZ 232
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#define TCK_1066MHZ 240
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#define TCK_1000MHZ 256
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#define TCK_933MHZ 274
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#define TCK_900MHZ 284
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#define TCK_800MHZ 320
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#define TCK_700MHZ 365
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#define TCK_666MHZ 384
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#define TCK_533MHZ 480
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#define TCK_400MHZ 640
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#define TCK_333MHZ 768
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#define TCK_266MHZ 960
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#define TCK_200MHZ 1280
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/** @} */
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/**
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* \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP
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*
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* Use this macro instead of printk(); for verbose RAM initialization messages.
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* When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically
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* disabled.
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* @{
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*/
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#if CONFIG(DEBUG_RAM_SETUP)
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#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
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#else
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#define printram(x, ...)
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#endif
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/** @} */
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/** Result of the SPD decoding process */
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enum spd_status {
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SPD_STATUS_OK = 0,
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SPD_STATUS_INVALID,
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SPD_STATUS_CRC_ERROR,
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SPD_STATUS_INVALID_FIELD,
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};
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u16 ddr_crc16(const u8 *ptr, int n_crc);
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#endif /* DEVICE_DRAM_COMMON_H */
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