bf0970e762
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
122 lines
3.0 KiB
C
122 lines
3.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017-2018 Facebook, Inc.
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* Copyright 2003-2017 Cavium Inc. (support@cavium.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
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*/
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#include <device/device.h>
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#include <libbdk-hal/bdk-config.h>
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#include <libbdk-hal/bdk-twsi.h>
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#include <soc/gpio.h>
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#include <soc/uart.h>
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#include <console/console.h>
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#include <soc/clock.h>
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#include <soc/timer.h>
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#include <soc/cpu.h>
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#include <soc/sdram.h>
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#include <soc/spi.h>
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#include <spi_flash.h>
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#include <fmap.h>
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static void mainboard_print_info(void)
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{
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struct region region;
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if (fmap_locate_area("WP_RO", ®ion) < 0) {
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printk(BIOS_ERR, "MB: Could not find region '%s'\n", "WP_RO");
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} else {
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const struct spi_flash *flash = boot_device_spi_flash();
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const bool prot = (flash != NULL) &&
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(spi_flash_is_write_protected(flash, ®ion) == 1);
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printk(BIOS_INFO, "MB: WP_RO is %swrite protected\n",
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prot ? "" : "not ");
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}
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printk(BIOS_INFO, "MB: trusted boot : %s\n",
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gpio_strap_value(10) ? "yes" : "no");
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const size_t boot_method = gpio_strap_value(0) |
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(gpio_strap_value(1) << 1) |
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(gpio_strap_value(2) << 2) |
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(gpio_strap_value(3) << 3);
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printk(BIOS_INFO, "MB: boot method : ");
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switch (boot_method) {
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case 0x2:
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case 0x3:
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printk(BIOS_INFO, "EMMC\n");
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break;
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case 0x5:
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case 0x6:
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printk(BIOS_INFO, "SPI\n");
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break;
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case 0x8:
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printk(BIOS_INFO, "REMOTE\n");
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break;
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case 0xc:
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case 0xd:
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printk(BIOS_INFO, "PCIe\n");
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break;
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default:
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printk(BIOS_INFO, "unknown\n");
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}
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printk(BIOS_INFO, "MB: REFclk : %llu MHz\n",
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thunderx_get_ref_clock() / 1000000ULL);
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printk(BIOS_INFO, "MB: IOclk : %llu MHz\n",
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thunderx_get_io_clock() / 1000000ULL);
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printk(BIOS_INFO, "MB: COREclk : %llu MHz\n",
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thunderx_get_core_clock() / 1000000ULL);
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printk(BIOS_INFO, "MB: #CPU cores : %zu\n",
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cpu_get_num_available_cores());
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printk(BIOS_INFO, "MB: RAM : %zu MiB\n",
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sdram_size_mb());
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printk(BIOS_INFO, "MB: SPIclk : %llu kHz\n",
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spi_get_clock(0) >> 10);
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}
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extern const struct bdk_devicetree_key_value devtree[];
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static void mainboard_init(struct device *dev)
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{
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size_t i;
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/* Init timer */
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soc_timer_init();
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/* Init CPUs */
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for (i = 1; i < CONFIG_MAX_CPUS; i++)
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start_cpu(i, NULL);
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = &mainboard_init;
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bdk_config_set_fdt(devtree);
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mainboard_print_info();
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}
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struct chip_operations mainboard_ops = {
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.name = CONFIG_MAINBOARD_PART_NUMBER,
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.enable_dev = mainboard_enable,
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};
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