bf0970e762
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <assert.h>
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#include <soc/addressmap.h>
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#include <soc/grf.h>
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#include <soc/soc.h>
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#include <soc/pwm.h>
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#include <soc/clock.h>
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#include <stdlib.h>
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#include <timer.h>
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struct pwm_ctl {
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u32 pwm_cnt;
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u32 pwm_period_hpr;
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u32 pwm_duty_lpr;
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u32 pwm_ctrl;
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};
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struct rk_pwm_regs {
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struct pwm_ctl pwm[4];
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u32 intsts;
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u32 int_en;
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};
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check_member(rk_pwm_regs, int_en, 0x44);
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#define RK_PWM_DISABLE (0 << 0)
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#define RK_PWM_ENABLE (1 << 0)
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#define PWM_ONE_SHOT (0 << 1)
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#define PWM_CONTINUOUS (1 << 1)
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#define RK_PWM_CAPTURE (1 << 2)
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#define PWM_DUTY_POSTIVE (1 << 3)
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#define PWM_DUTY_NEGATIVE (0 << 3)
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#define PWM_INACTIVE_POSTIVE (1 << 4)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_OUTPUT_CENTER (1 << 5)
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#define PWM_LP_ENABLE (1 << 8)
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#define PWM_LP_DISABLE (0 << 8)
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#define PWM_SEL_SCALE_CLK (1 << 9)
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#define PWM_SEL_SRC_CLK (0 << 9)
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struct rk_pwm_regs *rk_pwm = (void *)RK_PWM_BASE;
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void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
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{
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unsigned long period, duty;
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#if CONFIG(SOC_ROCKCHIP_RK3288)
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/*use rk pwm*/
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write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
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#endif
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write32(&rk_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
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PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS |
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PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
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period = (PWM_CLOCK_HZ / 1000) * period_ns / USECS_PER_SEC;
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duty = (PWM_CLOCK_HZ / 1000) * duty_ns / USECS_PER_SEC;
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write32(&rk_pwm->pwm[id].pwm_period_hpr, period);
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write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty);
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setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
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}
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