Files
system76-coreboot/src/soc
Andrey Petrov 335384d2b7 soc/intel/xeon_sp: Configure P2SB BAR in bootblock
In order to use early serial output we need to enable P2SB BAR0, because
that allows PCR access to PCH registers.

TEST=tested on OCP Tioga Pass

Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-26 02:53:26 +00:00
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