bfb11bec3b
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Driver for BayHub Technology LV2 PCI to SD bridge */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "lv2.h"
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/*
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* This chip has an errata where PCIe config space registers 0x234, 0x248, and
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* 0x24C only support DWORD access, therefore reprogram these in the `finalize`
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* callback.
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*/
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static void lv2_enable_ltr(struct device *dev)
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{
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u16 max_snoop, max_nosnoop;
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if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop))
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return;
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const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID, 0);
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if (!ltr_cap)
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return;
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pci_write_config32(dev, ltr_cap + PCI_LTR_MAX_SNOOP, (max_snoop << 16) | max_nosnoop);
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printk(BIOS_INFO, "%s: Re-programmed LTR max latencies using chip-specific quirk\n",
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dev_path(dev));
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}
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static void lv2_enable(struct device *dev)
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{
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struct drivers_generic_bayhub_lv2_config *config = dev->chip_info;
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pci_dev_init(dev);
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if (!config || !config->enable_power_saving)
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return;
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/*
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* This procedure for enabling power-saving mode is from the
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* BayHub BIOS Implementation Guideline document.
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*/
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pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF);
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pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE);
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pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER);
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pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
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pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
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pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
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pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
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LV2_L1_SUBSTATE_OPTIMISE);
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pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
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pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
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LV2_DRIVER_STRENGTH);
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pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
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LV2_RESET_DMA_DISABLE);
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pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
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printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n");
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}
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static struct device_operations lv2_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.ops_pci = &pci_dev_ops_pci,
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.enable = lv2_enable,
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.final = lv2_enable_ltr,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DID_O2_LV2,
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0
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};
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static const struct pci_driver bayhub_lv2 __pci_driver = {
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.ops = &lv2_ops,
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.vendor = PCI_VID_O2,
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.devices = pci_device_ids,
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};
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struct chip_operations drivers_generic_bayhub_lv2_ops = {
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.name = "BayHub Technology LV2 PCIe to SD bridge",
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};
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