c009601f29
Change-Id: I2ff70cafdd808a235ed4f0663e182d306f493c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
132 lines
4.0 KiB
C
Executable File
132 lines
4.0 KiB
C
Executable File
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "agesawrapper.h"
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#include "amdlib.h"
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#include "BiosCallOuts.h"
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#include "heapManager.h"
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#include "SB800.h"
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#include <cbfs.h>
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#include <string.h>
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#include <device/dram/ddr3.h>
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#define SPD_SIZE 128
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#define SPD_CRC_HI 127
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#define SPD_CRC_LO 126
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer },
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{AGESA_LOCATE_BUFFER, BiosLocateBuffer },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, BiosReadSpd_from_cbfs },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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UINTN i;
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AGESA_STATUS CalloutStatus;
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UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
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/*
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* printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func);
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*/
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CalloutStatus = AGESA_UNSUPPORTED;
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for (i = 0; i < CallOutCount; i++) {
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if (BiosCallouts[i].CalloutName == Func) {
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CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
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return CalloutStatus;
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}
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}
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return CalloutStatus;
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}
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AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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#ifdef __PRE_RAM__
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AGESA_READ_SPD_PARAMS *info = ConfigPtr;
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if (info->MemChannelId > 0)
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return AGESA_UNSUPPORTED;
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if (info->SocketId != 0)
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return AGESA_UNSUPPORTED;
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if (info->DimmId != 0)
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return AGESA_UNSUPPORTED;
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char *spd_file;
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size_t spd_file_len;
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printk(BIOS_DEBUG, "read SPD\n");
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spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
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&spd_file_len);
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if (!spd_file)
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die("file [spd.bin] not found in CBFS");
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if (spd_file_len < SPD_SIZE)
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die("Missing SPD data.");
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memcpy((char*)info->Buffer, spd_file, SPD_SIZE);
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u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE);
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if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0))
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|| (info->Buffer[SPD_CRC_LO] != (crc & 0xff))
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|| (info->Buffer[SPD_CRC_HI] != (crc >> 8))) {
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printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
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info->Buffer[SPD_CRC_LO] = crc & 0xff;
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info->Buffer[SPD_CRC_HI] = crc >> 8;
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u16 i;
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printk(BIOS_WARNING, "\nDisplay the SPD");
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for (i = 0; i < SPD_SIZE; i++) {
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if((i % 16) == 0x00)
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printk(BIOS_WARNING, "\n%02x: ",i);
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printk(BIOS_WARNING, "%02x ", info->Buffer[i]);
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}
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printk(BIOS_WARNING, "\n");
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}
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Status = AGESA_SUCCESS;
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#else
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Status = AGESA_UNSUPPORTED;
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#endif
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return Status;
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}
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/* Call the host environment interface to provide a user hook opportunity. */
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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// Unlike AMD/Inagua, this board is unable to vary the RAM voltage.
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// Make sure the right speed settings are selected.
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((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
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return AGESA_SUCCESS;
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}
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