Nico Huber c01d0920bb arch/riscv: Rename stages.c to romstage.c ...

It's only used for romstage and is incompatible to ramstages. The latter
get `cbmem_top` passed as a third argument now.

Also drop comments that don't apply to this file anymore.

Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

2019-11-06 13:57:12 +00:00

..

include

arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0

2019-09-09 22:17:27 +00:00

arch_timer.c

device/mmio.h: Add include file for MMIO ops

2019-03-04 15:57:39 +00:00

boot.c

riscv: add support for OpenSBI

2019-08-03 17:17:24 +00:00

bootblock.S

riscv: Add initial support for 32bit boards

2019-02-13 04:49:14 +00:00

fit_payload.c

src: Remove unused 'include <string.h>'

2019-10-20 17:19:34 +00:00

fp_asm.S

riscv: update misaligned memory access exception handling

2018-09-10 15:03:58 +00:00

Kconfig

riscv: add support for OpenSBI

2019-08-03 17:17:24 +00:00

Makefile.inc

arch/riscv: Rename stages.c to romstage.c

2019-11-06 13:57:12 +00:00

mcall.c

arch/riscv/mcall: Drop debug code

2019-06-28 07:35:56 +00:00

misaligned.c

src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode

2018-10-30 02:07:58 +00:00

misc.c

arch/riscv: provide a monotonic timer

2018-09-14 09:28:06 +00:00

opensbi.c

riscv: add support for OpenSBI

2019-08-03 17:17:24 +00:00

payload.c

riscv: add support for OpenSBI

2019-08-03 17:17:24 +00:00

pmp.c

riscv: add physical memory protection (PMP) support

2018-10-11 10:56:54 +00:00

ramstage.S

riscv: Add initial support for 32bit boards

2019-02-13 04:49:14 +00:00

romstage.c

arch/riscv: Rename stages.c to romstage.c

2019-11-06 13:57:12 +00:00

sbi.c

src: Use include <console/console.h> when appropriate

2019-04-23 10:01:21 +00:00

smp.c

riscv: Add initial support for 32bit boards

2019-02-13 04:49:14 +00:00

tables.c

riscv: add support for OpenSBI

2019-08-03 17:17:24 +00:00

trap_handler.c

src: Use 'include <string.h>' when appropriate

2019-03-20 20:27:51 +00:00

trap_util.S

arch/riscv: Align trap_entry to 4 bytes, as required by spec

2018-02-20 20:44:43 +00:00

virtual_memory.c

arch/riscv: Don't set FPU state to "dirty"

2018-12-19 05:46:07 +00:00