c027ece821
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
122 lines
2.9 KiB
Plaintext
122 lines
2.9 KiB
Plaintext
config SOUTHBRIDGE_INTEL_COMMON_RESET
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def_bool n
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select HAVE_CF9_RESET
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config SOUTHBRIDGE_INTEL_COMMON_RTC
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
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def_bool n
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depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
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config SOUTHBRIDGE_INTEL_COMMON_PMBASE
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_GPIO
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_ME
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_HPET
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMBUS
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def_bool n
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select HAVE_DEBUG_SMBUS
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config SOUTHBRIDGE_INTEL_COMMON_SPI
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def_bool n
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select SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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config HAVE_INTEL_CHIPSET_LOCKDOWN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMM
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def_bool n
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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select SOUTHBRIDGE_INTEL_COMMON_PMBASE
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config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
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bool
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config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
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bool
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config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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def_bool n
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select HAVE_USBDEBUG
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config INTEL_DESCRIPTOR_MODE_CAPABLE
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def_bool n
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help
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This config simply states that the platform is *capable* of running in
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descriptor mode (when the descriptor in flash is valid).
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config INTEL_DESCRIPTOR_MODE_REQUIRED
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def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE
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help
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This config states descriptor mode is *required* for the platform to
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function properly, or to function at all.
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config VALIDATE_INTEL_DESCRIPTOR
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depends on INTEL_DESCRIPTOR_MODE_CAPABLE
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bool "Validate Intel firmware descriptor"
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default n
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help
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This config enables validating the Intel firmware descriptor against the
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fmap layout. If the firmware descriptor layout does not match the fmap
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then the bootimage cannot be built.
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config INTEL_CHIPSET_LOCKDOWN
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depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
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#ChromeOS's payload seems to handle finalization on its on.
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bool "Lock down chipset in coreboot"
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default y
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help
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Some registers within host bridge on particular chipsets should be
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locked down on each normal boot path (done by either coreboot or payload)
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and S3 resume (always done by coreboot). Select this to let coreboot
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to do this on normal boot path.
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config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
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bool
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depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
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config FIXED_RCBA_MMIO_BASE
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hex
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default 0xfed1c000
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config RCBA_LENGTH
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hex
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default 0x4000
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config FIXED_SMBUS_IO_BASE
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hex
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depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
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default 0x400
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