c056d18fbe
The CPUID function to get the number of cores on a package is common across multiple generations of AMD cpus. Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/mca.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/smm.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/smi.h>
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#include <types.h>
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/*
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* MP and SMM loading initialization.
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*/
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/*
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* Do essential initialization tasks before APs can be fired up -
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*
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* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
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* creates the MTRR solution that the APs will use. Otherwise APs will try to
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* apply the incomplete solution as the BSP is calculating it.
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*/
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static void pre_mp_init(void)
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{
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const msr_t syscfg = rdmsr(SYSCFG_MSR);
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if (syscfg.lo & SYSCFG_MSR_TOM2WB)
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x86_setup_mtrrs_with_detect_no_above_4gb();
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else
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = global_smi_enable,
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};
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void mp_init_cpus(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"mp_init_with_smm failed. Halting.\n");
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/* The flash is now no longer cacheable. Reset to WP for performance. */
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mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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set_warm_reset_flag();
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}
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static void model_15_init(struct device *dev)
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{
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check_mca();
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/*
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* Per AMD, sync an undocumented MSR with the PSP base address.
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* Experiments showed that if you write to the MSR after it has
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* been previously programmed, it causes a general protection fault.
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* Also, the MSR survives warm reset and S3 cycles, so we need to
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* test if it was previously written before writing to it.
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*/
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msr_t psp_msr;
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uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
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psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
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psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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psp_msr = rdmsr(PSP_ADDR_MSR);
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if (psp_msr.lo == 0) {
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psp_msr.lo = psp_bar;
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wrmsr(PSP_ADDR_MSR, psp_msr);
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}
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x660f01 },
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{ X86_VENDOR_AMD, 0x670f00 },
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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