c06af9eb8b
The few remaining boards without CAR override this with select ROMCC. Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6172 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
38 lines
1.0 KiB
Plaintext
38 lines
1.0 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config CPU_INTEL_SLOT_1
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bool
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if CPU_INTEL_SLOT_1
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config SLOT_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_MODEL_65X
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select CPU_INTEL_MODEL_67X
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select CPU_INTEL_MODEL_68X
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select CPU_INTEL_MODEL_6BX
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select CPU_INTEL_MODEL_6XX
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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endif
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