system76-coreboot

Files

Karthikeyan Ramasubramanian c126084bc5 soc/intel: Add GPI interrupt config register offset info

Add the offset information for GPI interrupt status and enable register
in the pad_community structure. Populate the concerned information for
individual SoCs. This offset information is required to clear the
interrupt configuration during the bootup.

BUG=b:130593883
BRANCH=None
TEST=Ensure that the interrupt configuration are cleared during bootup.
Ensured that the system boots to ChromeOS.

Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2019-04-29 12:18:27 +00:00

acpi

soc/intel/common/acpi: Add dynamic method around sleep

2019-04-23 10:20:29 +00:00

basecode

soc/intel/common: Make infrastructure ready for Intel common stage files

2018-06-21 15:54:48 +00:00

block

soc/intel: Add GPI interrupt config register offset info

2019-04-29 12:18:27 +00:00

pch

src: Use 'include <string.h>' when appropriate