c14e961f23
This disables the spread spectrum clock and avoids errata. Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66673 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e) falco: Remove RTD2132 driver from kconfig Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2) Conflicts: src/mainboard/google/falco/Kconfig Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698 Reviewed-on: https://chromium-review.googlesource.com/167311 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3) Squashed two commits and corrected the subject line from 2312 to 2132. Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6527 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
122 lines
3.8 KiB
Plaintext
122 lines
3.8 KiB
Plaintext
chip northbridge/intel/haswell
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Disable DisplayPort C Hotplug
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register "gpu_dp_c_hotplug" = "0x00"
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# Enable HDMI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Set backlight PWM values for eDP
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register "gpu_cpu_backlight" = "0x00000200"
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register "gpu_pch_backlight" = "0x04000000"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4)
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register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2)
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register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7)
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5)
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6)
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/haswell
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
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register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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chip southbridge/intel/lynxpoint
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "ide_legacy_combined" = "0x0"
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register "sata_ahci" = "0x1"
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register "sata_port_map" = "0x1"
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register "sio_acpi_mode" = "0"
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register "sio_i2c0_voltage" = "0" # 3.3V
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register "sio_i2c1_voltage" = "0" # 3.3V
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# Force enable ASPM for PCIe Port 1
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register "pcie_port_force_aspm" = "0x01"
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# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013e0000"
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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device pci 15.1 on end # I2C0
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device pci 15.2 on end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip ec/google/chromeec
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# We only have one init function that
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# we need to call to initialize the
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# keyboard part of the EC.
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 on end # Thermal
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end
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end
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end
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