Matt Delco c1cb6da816 mb/google/poppy/variants/nocturne: enable eist ...

Enable Enhanced Intel SpeedStep (EIST) on nocturne.

Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2018-08-20 15:54:28 +00:00

..

acpi

arch/x86: Add common AMD ACPI hardware definitions

2017-11-10 19:15:38 +00:00

arch

arm64: Factor out common parts of romstage execution flow

2018-08-17 21:29:46 +00:00

commonlib

src/{commonlib,lib}: Fix typo

2018-08-16 18:55:08 +00:00

console

arch/x86: Drop leftover ROMCC console support

2018-06-08 03:31:12 +00:00

cpu

cpu/intel/common: add function to init cppc_config

2018-08-20 15:53:28 +00:00

device

nb/intel/sandybridge: Fill in DIMM serial number

2018-08-20 09:51:22 +00:00

drivers

drivers/pc80/rtc: do not warn if CMOS options are unavailable

2018-08-20 10:57:41 +00:00

ec

ec/lenovo/pmh7: use read/write function in clear_bit/set_bit

2018-08-20 06:57:18 +00:00

include

soc/intel/common/block: Add WHL 2-core SKU

2018-08-20 15:50:57 +00:00

lib

src/{commonlib,lib}: Fix typo

2018-08-16 18:55:08 +00:00

mainboard

mb/google/poppy/variants/nocturne: enable eist

2018-08-20 15:54:28 +00:00

northbridge

nb/intel/raminit: Remove unused headers

2018-08-20 09:52:08 +00:00

security

cr50: Allow boards to disable powering off EC on cr50 update

2018-08-17 12:27:23 +00:00

soc

soc/intel/skylake: add CPPC support

2018-08-20 15:53:54 +00:00

southbridge

Fix PCI ACPI _OSC methods

2018-08-17 21:09:17 +00:00

superio

superio/ite/it8720f: fix power control init

2018-08-17 18:27:00 +00:00

vendorcode

cr50: Allow boards to disable powering off EC on cr50 update

2018-08-17 12:27:23 +00:00

Kconfig

Kconfig: Make the EM100 config option common

2018-07-16 07:41:14 +00:00