66decf1644
Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
77 lines
2.6 KiB
HTML
77 lines
2.6 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>FSP 1.1</title>
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</head>
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<body>
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<h1>x86 FSP 1.1 Development</h1>
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<p>
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Firmware Support Package (FSP) development requires System-on-a-Chip (SoC)
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and board support. The combined steps are listed
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<a target="_blank" href="development.html">here</a>.
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The development steps for FSP are listed below:
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</p>
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<ol>
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<li><a href="#RequiredFiles">Required Files</a></li>
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<li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
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<li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
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</ol>
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<p>
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FSP Documentation:
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</p>
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<ul>
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<li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
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</ul>
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<hr>
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<h1><a name="RequiredFiles">Required Files</a></h1>
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<h2><a name="corebootRequiredFiles">coreboot Required Files</a></h2>
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<ol>
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<li>Create the following directories if they do not already exist:
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<ul>
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<li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li>
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<li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li>
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</ul>
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</li>
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<li>
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The following files may need to be copied from the FSP build or release into the
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directories above if they are not present or are out of date:
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<ul>
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<li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li>
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<li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li>
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</ul>
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</li>
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</ol>
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<hr>
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<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1>
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<p>
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Add the FSP binary to the coreboot flash image using the following command:
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</p>
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<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre>
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<p>
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This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
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FSP code for TempRamInit may be executed in place.
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</p>
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<hr>
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<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1>
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<p>
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Set the following Kconfig values:
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</p>
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<ul>
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<li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
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<li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
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<li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
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<li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
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</ul>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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</html> |