c2570dc998
This patch performs locking of the PMC soft strap message interface. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC MMIO register 0x104c is set as below. > localhost ~ # iotools mmio_read32 0xfe00104c 0x00000001 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
38 lines
960 B
C
38 lines
960 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 4
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*/
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#include <device/mmio.h>
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#include <intelblocks/cfg.h>
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#include <intelpch/lockdown.h>
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#include <soc/pm.h>
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#include <stdint.h>
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static void pmc_lockdown_cfg(int chipset_lockdown)
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{
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uint8_t *pmcbase = pmc_mmio_regs();
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/* PMSYNC */
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setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
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/* Lock down ABASE and sleep stretching policy */
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setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
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setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
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if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
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setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK);
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setbits32(pmcbase + SSML, SSML_SSL_EN);
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}
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}
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void soc_lockdown_config(int chipset_lockdown)
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{
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/* PMC lock down configuration */
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pmc_lockdown_cfg(chipset_lockdown);
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}
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