c28984d9ea
RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.
New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.
spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
137 lines
3.3 KiB
C
137 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <bootmode.h>
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#include <console/console.h>
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#include <string.h>
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#include <spi-generic.h>
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#include <spi_flash.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "nvm.h"
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#include "spi.h"
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/* This module assumes the flash is memory mapped just below 4GiB in the
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* address space for reading. Also this module assumes an area it erased
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* when all bytes read as all 0xff's. */
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static struct spi_flash *flash;
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static int nvm_init(void)
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{
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if (flash != NULL)
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return 0;
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spi_init();
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flash = spi_flash_probe(0, 0);
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if (!flash) {
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printk(BIOS_DEBUG, "Could not find SPI device\n");
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return -1;
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}
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return 0;
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}
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/*
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* Convert memory mapped pointer to flash offset.
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*
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* This is weak because not every platforms memory-maps the NVM media in the
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* same manner. This is a stop-gap solution.
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*
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* The root of the problem is that users of this API work in memory space for
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* both reads and writes, but erase and write must be done in flash space. This
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* also only works when the media is memory-mapped, which is no longer
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* universally true. The long-term approach should be to rewrite this and its
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* users to work in flash space, while using rdev_read() instead of rdev_mmap().
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*/
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__attribute__((weak))
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uint32_t nvm_mmio_to_flash_offset(void *p)
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{
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return CONFIG_ROM_SIZE + (uintptr_t)p;
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}
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int nvm_is_erased(const void *start, size_t size)
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{
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const uint8_t *cur = start;
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const uint8_t erased_value = 0xff;
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while (size > 0) {
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if (*cur != erased_value)
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return 0;
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cur++;
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size--;
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}
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return 1;
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}
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int nvm_erase(void *start, size_t size)
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{
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if (nvm_init() < 0)
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return -1;
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return spi_flash_erase(flash, nvm_mmio_to_flash_offset(start), size);
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}
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/* Write data to NVM. Returns 0 on success < 0 on error. */
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int nvm_write(void *start, const void *data, size_t size)
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{
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if (nvm_init() < 0)
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return -1;
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return spi_flash_write(flash, nvm_mmio_to_flash_offset(start), size,
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data);
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}
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/* Read flash status register to determine if write protect is active */
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int nvm_is_write_protected(void)
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{
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if (nvm_init() < 0)
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return -1;
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if (IS_ENABLED(CONFIG_CHROMEOS)) {
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u8 sr1;
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u8 wp_gpio;
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u8 wp_spi;
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/* Read Write Protect GPIO if available */
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wp_gpio = get_write_protect_state();
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/* Read Status Register 1 */
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if (spi_flash_status(flash, &sr1) < 0) {
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printk(BIOS_ERR,
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"Failed to read SPI status register 1\n");
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return -1;
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}
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wp_spi = !!(sr1 & 0x80);
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printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
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wp_gpio, wp_spi);
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return wp_gpio && wp_spi;
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}
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return 0;
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}
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/* Apply protection to a range of flash */
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int nvm_protect(void *start, size_t size)
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{
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#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT)
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if (nvm_init() < 0)
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return -1;
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return spi_flash_protect(nvm_mmio_to_flash_offset(start), size);
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#else
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return -1;
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#endif
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}
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