496362d7e1
Commit 45e4ab4a660c (mb/*: Update SPD mapping for sandybridge boards)
changed the way in which SPD addresses are set up for SNB/IVB boards,
but autoport was not updated to reflect these changes. Result is:
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" # FIXME: Put proper SPD map here"
The stray quote at the end is irritating, but is hard to get rid of
without substantial refactoring of autoport's guts. But, given that
this is a FIXME comment, anyone using autoport should just drop the
comment after verifying the SPD map, so it's not a big deal.
In addition, update the corresponding section of the README, which
was horrendously out-of-date.
Change-Id: I6ad38f53afc4fafb45be7f086723cc0782a965ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82405
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
104 lines
3.7 KiB
Go
104 lines
3.7 KiB
Go
package main
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import "fmt"
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import "strings"
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type sandybridgemc struct {
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}
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func MakeSPDMap(ctx Context) string {
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var values []string
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for _, addr := range GuessSPDMap(ctx) {
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values = append(values, fmt.Sprintf("0x%02x", addr))
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}
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return "{"+strings.Join(values, ", ")+"}"
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}
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func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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inteltool := ctx.InfoSource.GetInteltool()
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/* FIXME:XX Move this somewhere else. */
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MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
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MainboardEnable += (` /* FIXME: fix these values. */
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
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GMA_INT15_PANEL_FIT_DEFAULT,
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GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
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`)
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DevTree = DevTreeNode{
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Chip: "northbridge/intel/sandybridge",
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MissingParent: "northbridge",
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Comment: "FIXME: GPU registers may not always apply.",
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Registers: map[string]string{
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"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
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"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
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"gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
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"gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
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"gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
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"gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
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"gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
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"gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
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"gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
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"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
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"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
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"gfx": fmt.Sprintf("GMA_STATIC_DISPLAYS(%d)", (inteltool.IGD[0xc6200] >> 12) & 1),
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"spd_addresses": MakeSPDMap(ctx)+"\" # FIXME: Put proper SPD map here",
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},
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Children: []DevTreeNode{
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{
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Chip: "domain",
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Dev: 0,
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PCIController: true,
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ChildPCIBus: 0,
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"},
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},
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},
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},
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}
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PutPCIDev(addr, "Host bridge")
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/* FIXME:XX some configs are unsupported. */
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KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true
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KconfigBool["USE_NATIVE_RAMINIT"] = true
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KconfigBool["INTEL_INT15"] = true
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KconfigBool["HAVE_ACPI_TABLES"] = true
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KconfigBool["HAVE_ACPI_RESUME"] = true
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "cpu/intel/common/acpi/cpu.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "northbridge/intel/sandybridge/acpi/sandybridge.asl",
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}, DSDTInclude{
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File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
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})
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}
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func init() {
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RegisterPCI(0x8086, 0x0100, sandybridgemc{})
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RegisterPCI(0x8086, 0x0104, sandybridgemc{})
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RegisterPCI(0x8086, 0x0150, sandybridgemc{})
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RegisterPCI(0x8086, 0x0154, sandybridgemc{})
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RegisterPCI(0x8086, 0x0158, sandybridgemc{})
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for _, id := range []uint16{
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0x0102, 0x0106, 0x010a,
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0x0112, 0x0116, 0x0122, 0x0126,
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0x0152, 0x0156, 0x0162, 0x0166,
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} {
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RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}})
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}
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/* PCIe bridge */
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for _, id := range []uint16{
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0x0101, 0x0105, 0x0109, 0x010d,
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0x0151, 0x0155, 0x0159, 0x015d,
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} {
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RegisterPCI(0x8086, id, GenericPCI{})
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}
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}
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