Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
12 lines
363 B
Plaintext
12 lines
363 B
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
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Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
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/* AcpiGpe0Blk */
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OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
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Field(GP0B, ByteAcc, NoLock, Preserve) {
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, 11,
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USBS, 1,
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}
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