c31ba0ef52
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <arch/cpu.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/intel/common/util.h>
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#include <string.h>
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#include <timestamp.h>
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static void fsp_notify(enum fsp_notify_phase phase)
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{
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uint32_t ret;
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fsp_notify_fn fspnotify;
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struct fsp_notify_params notify_params = { .phase = phase };
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if (!fsps_hdr.notify_phase_entry_offset)
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die("Notify_phase_entry_offset is zero!\n");
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fspnotify = (void*) (fsps_hdr.image_base +
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fsps_hdr.notify_phase_entry_offset);
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fsp_before_debug_notify(fspnotify, ¬ify_params);
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if (phase == AFTER_PCI_ENUM) {
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timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
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post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
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} else if (phase == READY_TO_BOOT) {
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timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
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post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
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}
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ret = fspnotify(¬ify_params);
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if (phase == AFTER_PCI_ENUM) {
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timestamp_add_now(TS_FSP_AFTER_ENUMERATE);
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post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
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} else if (phase == READY_TO_BOOT) {
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timestamp_add_now(TS_FSP_AFTER_FINALIZE);
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post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
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}
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fsp_debug_after_notify(ret);
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/* Handle any errors returned by FspNotify */
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fsp_handle_reset(ret);
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if (ret != FSP_SUCCESS) {
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printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", ret);
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die("FspNotify returned an error!\n");
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}
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/* Allow the platform to run something after FspNotify */
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platform_fsp_notify_status(phase);
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}
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static void fsp_notify_dummy(void *arg)
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{
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enum fsp_notify_phase phase = (uint32_t)arg;
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/* Display the MTRRs */
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if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
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soc_display_mtrrs();
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fsp_notify(phase);
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if (phase == READY_TO_BOOT)
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fsp_notify(END_OF_FIRMWARE);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,
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(void *) AFTER_PCI_ENUM);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
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(void *) READY_TO_BOOT);
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
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(void *) READY_TO_BOOT);
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__attribute__((weak)) void platform_fsp_notify_status(
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enum fsp_notify_phase phase)
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{
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}
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