c36d506a05
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
121 lines
4.5 KiB
C
121 lines
4.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This code is based on src/mainboard/intel/jarrell/mptable.c */
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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u8 bus_pci = 6;
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u8 bus_pcie_a = 1;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LAPIC_ADDR);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &bus_isa);
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/* IOAPIC handling */
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smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
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mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
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/* Standard local interrupt assignments */
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x00);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* Internal PCI devices */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
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/* PCI slot */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pci, 0x00, 0x01, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pci, 0x01, 0x01, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pci, 0x02, 0x01, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pci, 0x03, 0x01, 0x13);
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/* PCIe port A slot */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pcie_a, 0x00, 0x01, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pcie_a, 0x01, 0x01, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pcie_a, 0x02, 0x01, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_pcie_a, 0x03, 0x01, 0x13);
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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