c36d506a05
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 AMD
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* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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* Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
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* (Thanks to LSRA University of Mannheim for their support)
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* Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdk8_sysconf.h>
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extern unsigned char bus_ck804[6];
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extern unsigned apicid_ck804;
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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unsigned sbdn;
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get_bus_conf();
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sbdn = sysconf.sbdn;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LAPIC_ADDR);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &bus_isa);
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/* I/O APICs: APIC ID Version State Address*/
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{
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device_t dev;
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struct resource *res;
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uint32_t dword;
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dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (res) {
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smp_write_ioapic(mc, apicid_ck804, 0x11,
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res->base);
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}
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/* Initialize interrupt mapping */
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/* copied from stock bios */
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/*0x01800500,0x1800d509,0x00520d08*/
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dword = 0x08d0d218;
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pci_write_config32(dev, 0x7c, dword);
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dword = 0x8d001509;
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pci_write_config32(dev, 0x80, dword);
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dword = 0x00010271;
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pci_write_config32(dev, 0x84, dword);
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}
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}
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/* Now, assemble the table. */
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mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
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bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin))
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#if 0
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// Onboard ck804 smbus
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PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */
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#endif
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// Onboard ck804 USB
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PCI_INT(0, sbdn+2, 0, 23);
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PCI_INT(0, sbdn+2, 1, 23);
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// Onboard ck804 AC-97
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PCI_INT(0, sbdn+4, 0, 23);
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// Onboard ck804 SATA 0
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PCI_INT(0, sbdn+7, 0, 20);
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// Onboard ck804 SATA 1
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PCI_INT(0, sbdn+8, 0, 21);
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// Onboard ck804 NIC
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PCI_INT(0, sbdn+10, 0, 22);
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/* "AGR" slot */
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PCI_INT(1, 0, 0, 16);
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PCI_INT(1, 0, 1, 17);
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/* legacy PCI */
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PCI_INT(1, 7, 0, 17);
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PCI_INT(1, 7, 1, 18);
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PCI_INT(1, 7, 2, 19);
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PCI_INT(1, 7, 3, 16);
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PCI_INT(1, 8, 0, 18);
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PCI_INT(1, 8, 1, 19);
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PCI_INT(1, 8, 2, 16);
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PCI_INT(1, 8, 3, 17);
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PCI_INT(1, 9, 0, 19);
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PCI_INT(1, 9, 1, 16);
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PCI_INT(1, 9, 2, 17);
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PCI_INT(1, 9, 3, 18);
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/* PCI-E x1 port */
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PCI_INT(2, 0, 0, 19);
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/* XXX guesses */
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PCI_INT(2, 0, 1, 16);
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PCI_INT(2, 0, 2, 17);
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PCI_INT(2, 0, 3, 18);
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/* PCI-E x16 port */ /* XXX fix me ? */
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PCI_INT(3, 0, 0, 18);
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/* XXX guesses */
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PCI_INT(3, 0, 1, 19);
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PCI_INT(3, 0, 2, 16);
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PCI_INT(3, 0, 3, 17);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
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smp_write_lintsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
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smp_write_lintsrc(mc, mp_NMI,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum =
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smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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