c36d506a05
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
142 lines
4.3 KiB
C
142 lines
4.3 KiB
C
#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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unsigned char bus_pxhd_1;
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unsigned char bus_pxhd_2;
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unsigned char bus_esb6300_1;
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unsigned char bus_esb6300_2;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LAPIC_ADDR);
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smp_write_processors(mc);
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{
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device_t dev;
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/* esb6300_2 */
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dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
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if (dev) {
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bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
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bus_esb6300_1 = 6;
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}
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/* esb6300_1 */
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dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
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if (dev) {
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bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
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bus_esb6300_2 = 7;
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}
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/* pxhd-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
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if (dev) {
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bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
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bus_pxhd_1 = 2;
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}
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/* pxhd-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
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if (dev) {
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bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_pxhd_2 = 3;
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}
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}
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mptable_write_buses(mc, NULL, &bus_isa);
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/* IOAPIC handling */
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smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
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smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
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{
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struct resource *res;
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device_t dev;
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/* PXHd apic 4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x04, 0x20, res->base);
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}
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
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printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
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}
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/* PXHd apic 5 */
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dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x05, 0x20, res->base);
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}
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} else {
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printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
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printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x00, 0x74, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x00, 0x77, 0x02, 0x17);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x00, 0x75, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x00, 0x7c, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x00, 0x7d, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
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0x03, 0x08, 0x05, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
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0x03, 0x08, 0x05, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
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bus_esb6300_1, 0x04, 0x03, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
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bus_esb6300_1, 0x08, 0x03, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
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bus_esb6300_2, 0x04, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
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bus_esb6300_2, 0x08, 0x02, 0x14);
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/* Standard local interrupt assignments */
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x00, MP_APIC_ALL, 0x00);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* FIXME verify I have the irqs handled for all of the risers */
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/* Compute the checksums */
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mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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