c391bff443
Instead of having the maximum number of possible CPU objects defined in the DSDT, dynamically generate the number of needed CPU devices in the SSDT like it's done on all other x86 platforms in coreboot. TEST=APU2 still boots and Linux doesn't show any ACPI errors with this patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
59 lines
1.5 KiB
Plaintext
59 lines
1.5 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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/* DefinitionBlock Statement */
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#include <acpi/acpi.h>
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DefinitionBlock (
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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#include <acpi/dsdt_top.asl>
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/* Globals for the platform */
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#include "acpi/mainboard.asl"
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/* Describe the USB Overcurrent pins */
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#include "acpi/usb_oc.asl"
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/* PCI IRQ mapping for the Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
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/* Contains the supported sleep states for this chipset */
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#include <southbridge/amd/common/acpi/sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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#include "acpi/routing.asl"
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/fch.asl>
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}
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/* Describe PCI INT[A-H] for the Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
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} /* End \_SB scope */
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/* Describe SMBUS for the Southbridge */
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#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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}
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/* End of ASL file */
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