c3cd6d7582
Change the default configuration for the following settings: AGPIO14: BT radio disable AGPIO64: NFC PU AGPIO65: NFC wake AGPIO66: Webcam AGPIO69: PCIe presence detect AGPIO70: GPS sleep AGPIO116: MUX for Power Express Eval EGPIO119: SD power Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4) Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17222 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
137 lines
4.7 KiB
C
137 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_def.h>
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#include <device/device.h>
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/pi/BiosCallOuts.h>
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#include <northbridge/amd/pi/00670F00/chip.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "FchPlatform.h"
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#include "cbfs.h"
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#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
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#include "imc.h"
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#endif
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#include "hudson.h"
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#include <stdlib.h>
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#include "BiosCallOuts.h"
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#include "northbridge/amd/pi/dimmSpd.h"
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#include "northbridge/amd/pi/agesawrapper.h"
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#include <PlatformMemoryConfiguration.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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static const GPIO_CONTROL oem_gardenia_gpio[] = {
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/* BT radio disable */
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{14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
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| FCH_GPIO_OUTPUT_ENABLE},
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/* NFC PU */
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{64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
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| FCH_GPIO_OUTPUT_ENABLE},
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/* NFC wake */
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{65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
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| FCH_GPIO_OUTPUT_ENABLE},
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/* Webcam */
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{66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
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| FCH_GPIO_OUTPUT_ENABLE},
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/* PCIe presence detect */
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{69, Function0, FCH_GPIO_PULL_UP_ENABLE},
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/* GPS sleep */
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{70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
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| FCH_GPIO_OUTPUT_ENABLE},
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/* MUX for Power Express Eval */
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{116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},
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/* SD power */
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{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
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| FCH_GPIO_OUTPUT_ENABLE},
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{-1}
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};
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such as Azalia, SATA, IMC etc.
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*/
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AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_reset->FchReset.Xhci1Enable = FALSE;
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FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
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oem_fan_control(FchParams_env);
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#endif
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/* XHCI configuration */
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#if CONFIG_HUDSON_XHCI_ENABLE
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FchParams_env->Usb.Xhci0Enable = TRUE;
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#else
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FchParams_env->Usb.Xhci0Enable = FALSE;
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#endif
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FchParams_env->Usb.Xhci1Enable = FALSE;
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FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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#ifdef __PRE_RAM__
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const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
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MOTHER_BOARD_LAYERS (LAYERS_6),
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MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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}
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#endif
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