c4301f7969
This patchs introduces level specific data cache maintenance operations to cache_helpers.S. It's derived form ARM trusted firmware repository. Please reference here. https://github.com/ARM-software/arm-trusted-firmware/blob/master/ lib/aarch64/cache_helpers.S BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82 Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9979 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
77 lines
2.3 KiB
ArmAsm
77 lines
2.3 KiB
ArmAsm
/*
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* Based on arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <arch/asm.h>
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#include <arch/cache_helpers.h>
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/*
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* Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a
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* known state regarding caches/SCTLR. Completely cleans and invalidates
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* icache/dcache, disables MMU and dcache (if active), and enables unaligned
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* accesses, icache and branch prediction (if inactive). Clobbers x4 and x5.
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*/
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ENTRY(arm_init_caches)
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/* w4: SCTLR, return address: x8 (stay valid for the whole function) */
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mov x8, x30
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/* XXX: Assume that we always start running at EL3 */
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mrs x4, sctlr_el3
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/* FIXME: How to enable branch prediction on ARMv8? */
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/* Flush and invalidate dcache */
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mov x0, #DCCISW
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bl flush_dcache_all
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/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
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and x4, x4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
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/* Activate ICache (12) already for speed */
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orr x4, x4, #(1 << 12)
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msr sctlr_el3, x4
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/* Invalidate icache and TLB for good measure */
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ic iallu
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tlbi alle3
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dsb sy
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isb
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ret x8
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ENDPROC(arm_init_caches)
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/* Based on u-boot transition.S */
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ENTRY(switch_el3_to_el2)
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mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */
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msr scr_el3, x0
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msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
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/* Return to the EL2_SP2 mode from EL3 */
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mov x0, sp
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msr sp_el2, x0 /* Migrate SP */
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mrs x0, vbar_el3
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msr vbar_el2, x0 /* Migrate VBAR */
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mrs x0, sctlr_el3
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msr sctlr_el2, x0 /* Migrate SCTLR */
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mov x0, #0x3c9
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msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */
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msr elr_el3, x30
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eret
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ENDPROC(switch_el3_to_el2)
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