ce22c02387
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <libpayload-config.h>
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#include <libpayload.h>
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#include <coreboot_tables.h>
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#include <multiboot_tables.h>
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/*
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* This is a global structure that is used through the library - we set it
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* up initially with some dummy values - hopefully they will be overridden.
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*/
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struct sysinfo_t lib_sysinfo = {
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.cpu_khz = 200,
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};
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int lib_get_sysinfo(void)
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{
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int ret;
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/* Get the CPU speed (for delays). */
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lib_sysinfo.cpu_khz = get_cpu_speed();
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/* Get information from the coreboot tables,
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* if they exist */
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ret = get_coreboot_info(&lib_sysinfo);
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/* If we can't get a good memory range, use the default. */
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if (!lib_sysinfo.n_memranges) {
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lib_sysinfo.n_memranges = 1;
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lib_sysinfo.memrange[0].base = 0;
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lib_sysinfo.memrange[0].size = 1024 * 1024;
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lib_sysinfo.memrange[0].type = CB_MEM_RAM;
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}
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return ret;
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}
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