c46242f904
This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.c4onc3_enable = 1,
^
/cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.p_cnt_throttling_supported = 1,
^
Change-Id: I691b51a97b359655c406bff28ee6562636d11015
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
79 lines
1.7 KiB
C
79 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
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#include <types.h>
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enum sata_mode {
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SATA_MODE_AHCI = 0,
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SATA_MODE_IDE_LEGACY_COMBINED,
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SATA_MODE_IDE_PLAIN,
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};
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struct southbridge_intel_i82801gx_config {
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/**
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/**
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* GPI Routing configuration
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*
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* Only the lower two bits have a meaning:
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* 00: No effect
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* 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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* 10: SCI (if corresponding GPIO_EN bit is also set)
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* 11: reserved
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*/
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uint8_t gpi0_routing;
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uint8_t gpi1_routing;
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uint8_t gpi2_routing;
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uint8_t gpi3_routing;
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uint8_t gpi4_routing;
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uint8_t gpi5_routing;
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uint8_t gpi6_routing;
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uint8_t gpi7_routing;
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uint8_t gpi8_routing;
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uint8_t gpi9_routing;
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uint8_t gpi10_routing;
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uint8_t gpi11_routing;
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uint8_t gpi12_routing;
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uint8_t gpi13_routing;
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uint8_t gpi14_routing;
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uint8_t gpi15_routing;
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uint32_t gpe0_en;
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uint16_t alt_gp_smi_en;
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/* IDE configuration */
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bool ide_enable_primary;
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bool ide_enable_secondary;
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enum sata_mode sata_mode;
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uint32_t sata_ports_implemented;
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/* Enable linear PCIe Root Port function numbers starting at zero */
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bool pcie_port_coalesce;
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bool c4onc3_enable;
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bool docking_supported;
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bool p_cnt_throttling_supported;
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int c3_latency;
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/* Additional LPC IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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};
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#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
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