c489a405d1
Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
220 lines
5.2 KiB
Plaintext
220 lines
5.2 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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# TODO: Update for mayan
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chip soc/amd/phoenix
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register "common_config.espi_config" = "{
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.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
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.generic_io_range[0] = {
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.base = 0x3f8,
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.size = 8,
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},
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.generic_io_range[1] = {
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.base = 0x600,
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.size = 256,
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},
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.io_mode = ESPI_IO_MODE_QUAD,
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.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
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.crc_check_enable = 1,
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.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
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.periph_ch_en = 1,
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.vw_ch_en = 1,
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.oob_ch_en = 1,
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.flash_ch_en = 0,
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}"
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register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
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GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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register "i2c[0].early_init" = "1"
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register "i2c[1].early_init" = "1"
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register "i2c[2].early_init" = "1"
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register "i2c[3].early_init" = "1"
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# I2C Pad Control RX Select Configuration
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register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
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register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
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register "s0ix_enable" = "true"
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register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
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register "usb_phy_custom" = "1"
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register "usb_phy" = "{
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.Usb2PhyPort[0] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[1] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[2] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[3] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[4] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[5] = {
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.compdistune = 0x3,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xe,
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.sqrxtune = 0x3,
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.txfslstune = 0x3,
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.txpreempamptune = 0x2,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb3PhyPort[0] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.Usb3PhyPort[1] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.Usb3PhyPort[2] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
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.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
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.BatteryChargerEnable = 0,
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.PhyP3CpmP4Support = 0,
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}"
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_OFF"
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register "gpp_clk_config[3]" = "GPP_CLK_REQ"
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device domain 0 on
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device ref iommu on end
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device ref gpp_bridge_2_1 on end # GBE
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device ref gpp_bridge_2_2 on end # WIFI
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device ref gpp_bridge_2_3 on end # NVMe SSD
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref gfx on end # Internal GPU (GFX)
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device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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device ref crypto on end # Crypto Coprocessor
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device ref xhci_0 on # USB 3.1 (USB0)
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chip drivers/usb/acpi
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device ref xhci_0_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port0 on end
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end
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chip drivers/usb/acpi
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port0 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port4 on end
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end
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end
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end
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end
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device ref xhci_1 on # USB 3.1 (USB1)
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chip drivers/usb/acpi
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device ref xhci_1_root_hub on
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chip drivers/usb/acpi
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device ref usb3_port5 on end
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end
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chip drivers/usb/acpi
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device ref usb2_port5 on end
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end
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end
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end
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end
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device ref acp on end # Audio Processor (ACP)
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end
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device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
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end
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end
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device ref i2c_0 on end
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device ref i2c_1 on end
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device ref i2c_2 on end
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device ref i2c_3 on end
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device ref uart_0 on end # UART0
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end
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