593124d520
Change-Id: Ia3de79c7d71049da00ed108829eac6cb49ff3ed6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41205 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#include <types.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <acpi/acpi.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
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* them for both DP and FDI transports, allowing those ports to
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* automatically adapt to HDMI connections as well.
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*/
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static u32 hsw_ddi_translations_dp[] = {
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0x00FFFFFF, 0x0006000E, /* DP parameters */
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0x00D75FFF, 0x0005000A,
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0x00C30FFF, 0x00040006,
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0x80AAAFFF, 0x000B0000,
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0x00FFFFFF, 0x0005000A,
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0x00D75FFF, 0x000C0004,
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0x80C30FFF, 0x000B0000,
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0x00FFFFFF, 0x00040006,
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0x80D75FFF, 0x000B0000,
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0x00FFFFFF, 0x00040006 /* HDMI parameters */
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};
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static u32 hsw_ddi_translations_fdi[] = {
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0x00FFFFFF, 0x0007000E, /* FDI parameters */
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0x00D75FFF, 0x000F000A,
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0x00C30FFF, 0x00060006,
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0x00AAAFFF, 0x001E0000,
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0x00FFFFFF, 0x000F000A,
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0x00D75FFF, 0x00160004,
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0x00C30FFF, 0x001E0000,
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0x00FFFFFF, 0x00060006,
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0x00D75FFF, 0x001E0000,
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0x00FFFFFF, 0x00040006 /* HDMI parameters */
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};
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/* On Haswell, DDI port buffers must be programmed with correct values
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* in advance. The buffer values are different for FDI and DP modes,
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* but the HDMI/DVI fields are shared among those. So we program the DDI
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* in either FDI or DP modes only, as HDMI connections will work with both
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* of those.
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*/
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static void intel_prepare_ddi_buffers(int port, int use_fdi_mode)
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{
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u32 reg;
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int i;
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u32 *ddi_translations = ((use_fdi_mode) ?
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hsw_ddi_translations_fdi :
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hsw_ddi_translations_dp);
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printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n",
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port,
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use_fdi_mode ? "FDI" : "DP");
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for (i=0,reg=DDI_BUF_TRANS(port);i < ARRAY_SIZE(hsw_ddi_translations_fdi);i++) {
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gtt_write(reg,ddi_translations[i]);
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reg += 4;
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}
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}
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void intel_prepare_ddi(void)
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{
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int port;
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u32 use_fdi = 1;
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for (port = PORT_A; port < PORT_E; port++)
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intel_prepare_ddi_buffers(port, !use_fdi);
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intel_prepare_ddi_buffers(PORT_E, use_fdi);
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}
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