c4e652ff57
1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <intelblocks/pmclib.h>
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#include <string.h>
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#include <soc/iomap.h>
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#include <soc/pch.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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void southbridge_smm_clear_state(void)
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{
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u32 smi_en;
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);
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smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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/* Dump and clear status registers */
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pmc_clear_smi_status();
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pmc_clear_pm1_status();
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pmc_clear_tco_status();
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pmc_clear_all_gpe_status();
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}
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void southbridge_smm_enable_smi(void)
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{
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printk(BIOS_DEBUG, "Enabling SMIs.\n");
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/* Configure events */
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pmc_enable_pm1(GBL_EN);
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pmc_disable_std_gpe(PME_B0_EN);
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/*
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* Enable SMI generation:
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* - on eSPI events (does nothing on LPC systems)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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* - on TCO events
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*/
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pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((u32)gnvs),
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"d" (APM_CNT)
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);
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}
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static void pm1_enable_pwrbtn_smi(void *unused)
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{
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/*
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* Enable power button SMI only before jumping to payload. This ensures
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* that:
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* 1. Power button SMI is enabled only after coreboot is done.
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* 2. On resume path, power button SMI is not enabled and thus avoids
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* any shutdowns because of power button presses due to power button
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* press in resume path.
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*/
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pmc_update_pm1_enable(PWRBTN_EN);
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}
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
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