c515898b33
This change adds and updates headers in all of the soc files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all soc directories. Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
159 lines
4.6 KiB
C
159 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <inttypes.h>
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#include <soc/addressmap.h>
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#include <soc/dma.h>
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#include <stddef.h>
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#include <stdlib.h>
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struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
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#define APB_DMA_OFFSET(n) \
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(struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n)
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struct apb_dma_channel apb_dma_channels[] = {
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{ .num = 0, .regs = APB_DMA_OFFSET(0x1000) },
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{ .num = 1, .regs = APB_DMA_OFFSET(0x1040) },
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{ .num = 2, .regs = APB_DMA_OFFSET(0x1080) },
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{ .num = 3, .regs = APB_DMA_OFFSET(0x10c0) },
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{ .num = 4, .regs = APB_DMA_OFFSET(0x1100) },
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{ .num = 5, .regs = APB_DMA_OFFSET(0x1140) },
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{ .num = 6, .regs = APB_DMA_OFFSET(0x1180) },
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{ .num = 7, .regs = APB_DMA_OFFSET(0x11c0) },
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{ .num = 8, .regs = APB_DMA_OFFSET(0x1200) },
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{ .num = 9, .regs = APB_DMA_OFFSET(0x1240) },
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{ .num = 10, .regs = APB_DMA_OFFSET(0x1280) },
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{ .num = 11, .regs = APB_DMA_OFFSET(0x12c0) },
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{ .num = 12, .regs = APB_DMA_OFFSET(0x1300) },
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{ .num = 13, .regs = APB_DMA_OFFSET(0x1340) },
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{ .num = 14, .regs = APB_DMA_OFFSET(0x1380) },
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{ .num = 15, .regs = APB_DMA_OFFSET(0x13c0) },
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{ .num = 16, .regs = APB_DMA_OFFSET(0x1400) },
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{ .num = 17, .regs = APB_DMA_OFFSET(0x1440) },
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{ .num = 18, .regs = APB_DMA_OFFSET(0x1480) },
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{ .num = 19, .regs = APB_DMA_OFFSET(0x14c0) },
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{ .num = 20, .regs = APB_DMA_OFFSET(0x1500) },
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{ .num = 21, .regs = APB_DMA_OFFSET(0x1540) },
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{ .num = 22, .regs = APB_DMA_OFFSET(0x1580) },
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{ .num = 23, .regs = APB_DMA_OFFSET(0x15c0) },
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{ .num = 24, .regs = APB_DMA_OFFSET(0x1600) },
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{ .num = 25, .regs = APB_DMA_OFFSET(0x1640) },
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{ .num = 26, .regs = APB_DMA_OFFSET(0x1680) },
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{ .num = 27, .regs = APB_DMA_OFFSET(0x16c0) },
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{ .num = 28, .regs = APB_DMA_OFFSET(0x1700) },
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{ .num = 29, .regs = APB_DMA_OFFSET(0x1740) },
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{ .num = 30, .regs = APB_DMA_OFFSET(0x1780) },
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{ .num = 31, .regs = APB_DMA_OFFSET(0x17c0) },
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};
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int dma_busy(struct apb_dma_channel * const channel)
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{
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/*
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* In continuous mode, the BSY_n bit in APB_DMA_STATUS and
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* BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long
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* as the channel is enabled. So for this function we'll use the
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* DMA_ACTIVITY bit in case of continuous mode.
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*
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* However, for ONCE mode, the BSY_n bit in APB_DMA_STATUS will be used
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* to determine end of dma operation.
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*/
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uint32_t bit;
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if (read32(&channel->regs->csr) & APB_CSR_ONCE)
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/* Once mode */
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bit = APB_STA_BSY;
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else
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/* Continuous mode */
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bit = APB_STA_DMA_ACTIVITY;
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return read32(&channel->regs->sta) & bit ? 1 : 0;
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}
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/* claim a DMA channel */
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struct apb_dma_channel * const dma_claim(void)
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{
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int i;
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struct apb_dma_channel_regs *regs = NULL;
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/*
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* Set global enable bit, otherwise register access to channel
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* DMA registers will not be possible.
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*/
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setbits_le32(&apb_dma->command, APB_COMMAND_GEN);
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for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
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regs = apb_dma_channels[i].regs;
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if (!apb_dma_channels[i].in_use) {
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u32 status = read32(®s->sta);
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if (status & (1 << i)) {
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/* FIXME: should this be fatal? */
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printk(BIOS_DEBUG, "%s: DMA channel %d busy?\n",
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__func__, i);
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}
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break;
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}
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}
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if (i == ARRAY_SIZE(apb_dma_channels))
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return NULL;
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apb_dma_channels[i].in_use = 1;
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return &apb_dma_channels[i];
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}
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/* release a DMA channel */
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void dma_release(struct apb_dma_channel * const channel)
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{
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int i;
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/* FIXME: make this "thread" friendly */
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while (dma_busy(channel))
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;
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channel->in_use = 0;
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/* clear the global enable bit if no channels are in use */
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for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
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if (apb_dma_channels[i].in_use)
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return;
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}
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clrbits_le32(&apb_dma->command, APB_COMMAND_GEN);
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}
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int dma_start(struct apb_dma_channel * const channel)
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{
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struct apb_dma_channel_regs *regs = channel->regs;
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/* Set ENB bit for this channel */
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setbits_le32(®s->csr, APB_CSR_ENB);
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return 0;
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}
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int dma_stop(struct apb_dma_channel * const channel)
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{
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struct apb_dma_channel_regs *regs = channel->regs;
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/* Clear ENB bit for this channel */
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clrbits_le32(®s->csr, APB_CSR_ENB);
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return 0;
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}
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