c56c723deb
Most boards use `device lapic 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
92 lines
3.0 KiB
Plaintext
92 lines
3.0 KiB
Plaintext
chip northbridge/intel/sandybridge
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# IGD Displays
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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# Enable DisplayPort B Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
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register "gpu_panel_power_cycle_delay" = "5" # 400ms
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register "gpu_panel_power_up_delay" = "500" # 50ms
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register "gpu_panel_power_down_delay" = "150" # 15ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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# Set backlight PWM values
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register "gpu_cpu_backlight" = "0x000001d4"
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register "gpu_pch_backlight" = "0x03aa0000"
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register "max_mem_clock_mhz" = "666"
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0 on end
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device lapic 0xacac off end
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register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
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register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3)
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register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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# Set Lid Switch to SMI to capture in recovery mode. It gets reset to
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# SCI mode when we go to ACPI mode.
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register "alt_gp_smi_en" = "0x8100"
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register "gpi7_routing" = "2"
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register "gpi8_routing" = "1"
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register "gpi15_routing" = "1" #lid switch gpe
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register "sata_port_map" = "0x1"
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# EC range is 0xFD60 (EC_IO) and 0x68/0x6C
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register "gen1_dec" = "0x0004fd61"
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register "gen2_dec" = "0x00040069"
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "1"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2 (WLAN)
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device pci 1c.2 on end # PCIe Port #3 (ETH0)
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip ec/compal/ene932
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# 60/64 KBC
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 on end # Thermal
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end
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end
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end
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