c5d6af43fb
Of the 13 mainboards that implement mainboard_should_reset_usb() hook, all but one do the same: Stop MRC from resetting USB when resuming from S3 suspend. This hook turns out is only here to facilitate a USB reset workaround on samsung/stumpy for an old ChromeOS kernel which is no longer needed. Drop the workaround, the hook, and headers no longer used. roda/rv11/early_init.c is left with no useful code after this patch, so drop it entirely from both bootblock and romstage. Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
80 lines
1.9 KiB
C
80 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
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#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
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/* Device ID for SandyBridge and IvyBridge */
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#define BASE_REV_SNB 0x00
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#define BASE_REV_IVB 0x50
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#define BASE_REV_MASK 0x50
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#include "memmap.h"
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ASSEMBLER__
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#include <types.h>
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/* Chipset types */
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enum platform_type {
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PLATFORM_MOBILE = 0,
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PLATFORM_DESKTOP_SERVER,
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};
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#include "registers/host_bridge.h"
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/* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */
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#define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define MSAC 0x62 /* Multi Size Aperture Control */
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/*
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* MCHBAR
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*/
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#include <northbridge/intel/common/fixed_bars.h>
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/* As there are many registers, define them on a separate file */
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#include "registers/mchbar.h"
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/*
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* EPBAR - Egress Port Root Complex Register Block
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*/
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#include "registers/epbar.h"
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/*
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* DMIBAR
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*/
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#include "registers/dmibar.h"
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bool is_sandybridge(void);
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void intel_sandybridge_finalize_smm(void);
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void systemagent_early_init(void);
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void sandybridge_init_iommu(void);
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void sandybridge_late_initialization(void);
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void northbridge_romstage_finalize(void);
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void early_init_dmi(void);
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/* mainboard_early_init: Optional callback, run after console init but before raminit. */
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void mainboard_early_init(int s3resume);
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void perform_raminit(int s3resume);
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void report_memory_config(void);
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enum platform_type get_platform_type(void);
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#include <device/device.h>
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struct acpi_rsdp;
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unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
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struct acpi_rsdp *rsdp);
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#endif /* __ASSEMBLER__ */
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#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */
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