857d3781e2
Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
127 lines
3.9 KiB
C
127 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <libpayload.h>
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#include <pci.h>
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/*
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* iATU Unroll-specific register definitions
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0C
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#define PCIE_ATU_UNR_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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#define PCIE_ATU_REGION_INDEX0 0x0
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#define PCIE_ATU_TYPE_CFG0 0x4
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#define PCIE_ATU_TYPE_CFG1 0x5
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#define PCIE_ATU_ENABLE BIT(31)
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#define ATU_CTRL2 PCIE_ATU_UNR_REGION_CTRL2
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#define ATU_ENABLE PCIE_ATU_ENABLE
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define LINK_WAIT_IATU_US 1000
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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/* Register address builder */
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
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#define lower_32_bits(n) ((u32)(n))
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#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
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/*
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* ATU & endpoint config space base address offsets relative to
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* PCIe controller base address.
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*/
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#define QCOM_ATU_BASE_OFFSET 0x1000
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#define QCOM_EP_CFG_OFFSET 0x100000
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#define QCOM_EP_CFG_SIZE 0x1000 /* 4K */
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static void dw_pcie_writel_iatu(void *atu_base, unsigned short index,
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uint32_t reg, uint32_t val)
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{
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uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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write32(atu_base + offset + reg, val);
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}
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static uint32_t dw_pcie_readl_iatu(void *atu_base, unsigned short index,
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uint32_t reg)
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{
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uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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return read32(atu_base + offset + reg);
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}
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static void dw_pcie_prog_outbound_atu(void *atu_base, unsigned short index,
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unsigned int type, uint64_t cfg_addr,
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uint64_t pcie_addr, uint32_t cfg_size)
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{
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cfg_addr));
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cfg_addr));
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LIMIT,
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lower_32_bits(cfg_addr + cfg_size - 1));
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pcie_addr));
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pcie_addr));
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_REGION_CTRL1, type);
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dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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if (retry(LINK_WAIT_MAX_IATU_RETRIES,
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(dw_pcie_readl_iatu(atu_base, index, ATU_CTRL2) & ATU_ENABLE),
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udelay(LINK_WAIT_IATU_US)))
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return;
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printf("outbound iATU is couldn't be enabled after 5ms\n");
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}
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/* Get PCIe MMIO configuration space base address */
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uintptr_t pci_map_bus(pcidev_t dev)
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{
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unsigned int atu_type, busdev;
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uint32_t config_size;
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void *cntrlr_base, *config_base, *atu_base;
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unsigned int current_bus = PCI_BUS(dev);
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unsigned int devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev);
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static pcidev_t current_dev;
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/*
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* Extract PCIe controller base from coreboot and derive the ATU and
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* endpoint config base addresses from it.
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*/
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cntrlr_base = (void *)lib_sysinfo.pcie_ctrl_base;
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config_base = (void *)cntrlr_base + QCOM_EP_CFG_OFFSET;
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config_size = (uint32_t)QCOM_EP_CFG_SIZE;
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atu_base = (void *)cntrlr_base + QCOM_ATU_BASE_OFFSET;
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/*
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* Cache the dev. For same dev, ATU mapping is not needed for each
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* request.
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*/
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if (current_dev == dev)
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goto out;
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current_dev = dev;
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busdev = PCIE_ATU_BUS(current_bus) |
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PCIE_ATU_DEV(PCI_SLOT(dev)) |
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PCIE_ATU_FUNC(PCI_FUNC(dev));
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atu_type = current_bus == 1 ? PCIE_ATU_TYPE_CFG0 : PCIE_ATU_TYPE_CFG1;
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dw_pcie_prog_outbound_atu(atu_base, PCIE_ATU_REGION_INDEX0, atu_type,
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(uint64_t)config_base, busdev, config_size);
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out:
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return (uintptr_t)config_base + (QCOM_EP_CFG_SIZE * devfn);
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}
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