Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
569 lines
17 KiB
Plaintext
569 lines
17 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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config SOC_INTEL_ALDERLAKE
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bool
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_X86
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_COMMON
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_SUPPORTS_INTEL_TME
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select CPU_SUPPORTS_PM_TIMER_EMULATION
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select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
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select DISPLAY_FSP_VERSION_INFO
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select DRIVERS_USB_ACPI
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select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
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select FSP_COMPRESS_FSP_S_LZ4
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select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
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select FSP_M_XIP
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select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
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select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
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select FSP_USES_CB_DEBUG_EVENT_HANDLER
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select FSPS_HAS_ARCH_UPD
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select GENERIC_GPIO_LIB
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select HAVE_DEBUG_RAM_SETUP
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select HAVE_FSP_GOP
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select HAVE_HYPERTHREADING
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select INTEL_GMA_OPREGION_2_1
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select INTEL_GMA_VERSION_2
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select INTEL_TXT_LIB
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select MP_SERVICES_PPI_V2
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select MRC_SETTINGS_PROTECT
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_2
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select SOC_INTEL_COMMON
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select CPU_INTEL_COMMON_VOLTAGE
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BASECODE
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select SOC_INTEL_COMMON_BASECODE_RAMTOP
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
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select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
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select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
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select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
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select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
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select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CNVI
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
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select SOC_INTEL_COMMON_BLOCK_DTT
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
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select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S
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select SOC_INTEL_COMMON_BLOCK_IRQ
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select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16
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select SOC_INTEL_COMMON_BLOCK_MEMINIT
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select SOC_INTEL_COMMON_BLOCK_OC_WDT
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select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
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select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
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select SOC_INTEL_COMMON_BLOCK_VTD
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select SOC_INTEL_COMMON_BLOCK_XHCI
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON
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select SOC_INTEL_CSE_SET_EOP
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select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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select HAVE_INTEL_COMPLIANCE_TEST_MODE
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N
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select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N
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select VBOOT_LIB
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select X86_CLFLUSH_CAR
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help
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Intel Alderlake support. Mainboards should specify the PCH
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type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
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of selecting this option directly.
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config SOC_INTEL_RAPTORLAKE
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bool
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select X86_INIT_NEED_1_SIPI
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help
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Intel Raptorlake support. Mainboards using RPL should select
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SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together.
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config SOC_INTEL_TWINLAKE
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bool
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select SOC_INTEL_ALDERLAKE_PCH_N
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help
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Intel Twinlake support. Mainboards using TWL should select
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SOC_INTEL_TWINLAKE.
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config SOC_INTEL_ALDERLAKE_PCH_N
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bool
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select HAVE_INTEL_FSP_REPO if !SOC_INTEL_TWINLAKE
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select SOC_INTEL_ALDERLAKE
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help
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Choose this option if your mainboard has a PCH-N chipset.
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config SOC_INTEL_ALDERLAKE_PCH_P
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bool
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select SOC_INTEL_ALDERLAKE
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select HAVE_INTEL_FSP_REPO
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select PLATFORM_USES_FSP2_3
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help
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Choose this option if your mainboard has a PCH-P chipset.
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config SOC_INTEL_ALDERLAKE_PCH_S
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bool
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select SOC_INTEL_ALDERLAKE
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select HAVE_INTEL_FSP_REPO
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select PLATFORM_USES_FSP2_3
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help
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Choose this option if your mainboard has a PCH-S chipset.
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config SOC_INTEL_RAPTORLAKE_PCH_S
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bool
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select SOC_INTEL_ALDERLAKE_PCH_S
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select SOC_INTEL_RAPTORLAKE
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help
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Choose this option if your mainboard has a Raptor Lake PCH-S chipset.
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if SOC_INTEL_ALDERLAKE
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config DIMM_SPD_SIZE
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default 512
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config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT
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bool
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default n if SOC_INTEL_ALDERLAKE_PCH_S
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default y
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select SOC_INTEL_COMMON_BLOCK_TCSS
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select SOC_INTEL_COMMON_BLOCK_USB4
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select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
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select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
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config ALDERLAKE_CONFIGURE_DESCRIPTOR
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bool
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help
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Select this if the descriptor needs to be updated at runtime. This
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can only be done if the descriptor region is writable, and should only
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be used as a temporary workaround.
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config ALDERLAKE_CAR_ENHANCED_NEM
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bool
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default y if !INTEL_CAR_NEM
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select INTEL_CAR_NEM_ENHANCED
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select CAR_HAS_SF_MASKS
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select COS_MAPPED_TO_MSB
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select CAR_HAS_L3_PROTECTED_WAYS
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config MAX_CPUS
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int
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default 32 if SOC_INTEL_RAPTORLAKE
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default 24
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0xc0000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x80400
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages. In the case of FSP_USES_CB_STACK default value will be
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sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
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(~1KiB).
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x20000
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help
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The amount of anticipated heap usage in CAR by FSP.
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Refer to Platform FSP integration guide document to know
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the exact FSP requirement for Heap setup.
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config CHIPSET_DEVICETREE
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string
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default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S
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default "soc/intel/alderlake/chipset.cb"
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config EXT_BIOS_WIN_BASE
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default 0xf8000000
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config EXT_BIOS_WIN_SIZE
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default 0x2000000
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config IFD_CHIPSET
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string
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default "adl"
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config IED_REGION_SIZE
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hex
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default 0x400000
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config GFX_GMA_DEFAULT_MMIO
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default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
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# Intel recommends reserving the following resources per PCIe TBT root port,
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# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5
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# - 42 buses
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# - 194 MiB Non-prefetchable memory
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# - 448 MiB Prefetchable memory
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if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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config PCIEXP_HOTPLUG_BUSES
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int
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default 42
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config PCIEXP_HOTPLUG_MEM
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hex
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default 0xc200000
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config PCIEXP_HOTPLUG_PREFETCH_MEM
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hex
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default 0x1c000000
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endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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config MAX_PCH_ROOT_PORTS
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int
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default 12 if SOC_INTEL_ALDERLAKE_PCH_N
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default 12 if SOC_INTEL_ALDERLAKE_PCH_P
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default 28 if SOC_INTEL_ALDERLAKE_PCH_S
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config MAX_CPU_ROOT_PORTS
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int
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default 0 if SOC_INTEL_ALDERLAKE_PCH_N
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default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S
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config MAX_TBT_ROOT_PORTS
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int
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default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S
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default 4 if SOC_INTEL_ALDERLAKE_PCH_P
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config MAX_ROOT_PORTS
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int
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default MAX_PCH_ROOT_PORTS
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config MAX_PCIE_CLOCK_SRC
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int
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default 5 if SOC_INTEL_ALDERLAKE_PCH_N
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default 10 if SOC_INTEL_ALDERLAKE_PCH_P
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default 18 if SOC_INTEL_ALDERLAKE_PCH_S
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help
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With external clock buffer, Alderlake-P can support up to three additional source clocks.
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This is done by setting the corresponding GPIO pin(s) to native function to use as
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SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock.
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If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on.
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config MAX_PCIE_CLOCK_REQ
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int
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default 5 if SOC_INTEL_ALDERLAKE_PCH_N
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default 10 if SOC_INTEL_ALDERLAKE_PCH_P
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default 18 if SOC_INTEL_ALDERLAKE_PCH_S
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x200000
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config PCR_BASE_ADDRESS
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hex
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default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xc0000000
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config CPU_BCLK_MHZ
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int
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default 100
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config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR
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int
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default 127
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config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR
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int
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default 100
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config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
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int
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default 120
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config CPU_XTAL_HZ
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default 38400000
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config SOC_INTEL_UFS_CLK_FREQ_HZ
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int
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default 19200000
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 133
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 7
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config SOC_INTEL_I2C_DEV_MAX
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int
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default 8
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config ENABLE_SATA_TEST_MODE
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bool "Enable test mode for SATA margining"
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default n
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help
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Enable SATA test mode in FSP-S.
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config SOC_INTEL_UART_DEV_MAX
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int
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default 7
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config CONSOLE_UART_BASE_ADDRESS
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hex
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default 0xfe03e000
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depends on INTEL_LPSS_UART_FOR_CONSOLE
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# Clock divider parameters for 115200 baud rate
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# Baudrate = (UART source clock * M) /(N *16)
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# ADL UART source clock: 100MHz
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x25a
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0x7fff
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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select VBOOT_X86_SHA256_ACCELERATION
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# Default hash block size is 1KiB. Increasing it to 4KiB to improve
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# hashing time as well as read time. This helps in improving
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# boot time for Alder Lake.
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config VBOOT_HASH_BLOCK_SIZE
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hex
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default 0x1000
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config CBFS_SIZE
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default 0x400000
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x4000
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config CONSOLE_CBMEM_BUFFER_SIZE
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hex
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default 0x100000 if BUILDING_WITH_DEBUG_FSP
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default 0x40000
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config FSP_TYPE_IOT
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bool
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default n
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help
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This option allows to select FSP IOT type from 3rdparty/fsp repo
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config FSP_HEADER_PATH
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string "Location of FSP headers"
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default "src/vendorcode/intel/fsp/fsp2_0/twinlake/" if SOC_INTEL_TWINLAKE && !FSP_USE_REPO
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default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO
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default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
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default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT
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default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
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default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
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default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S
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default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if SOC_INTEL_ALDERLAKE_PCH_N
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default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO
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config FSP_FD_PATH
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string
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depends on FSP_USE_REPO
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default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT
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default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
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default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
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default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
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default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_N
|
|
|
|
config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
|
|
int "Debug Consent for ADL"
|
|
# USB DBC is more common for developers so make this default to 2 if
|
|
# SOC_INTEL_DEBUG_CONSENT=y
|
|
default 2 if SOC_INTEL_DEBUG_CONSENT
|
|
default 0
|
|
help
|
|
This is to control debug interface on SOC.
|
|
Setting non-zero value will allow to use DBC or DCI to debug SOC.
|
|
PlatformDebugConsent in FspmUpd.h has the details.
|
|
|
|
Desired platform debug type are
|
|
0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
|
|
7:Manual
|
|
|
|
config DATA_BUS_WIDTH
|
|
int
|
|
default 128
|
|
|
|
config DIMMS_PER_CHANNEL
|
|
int
|
|
default 2
|
|
|
|
config MRC_CHANNEL_WIDTH
|
|
int
|
|
default 16
|
|
|
|
config ALDERLAKE_ENABLE_SOC_WORKAROUND
|
|
bool
|
|
default y
|
|
select SOC_INTEL_UFS_LTR_DISQUALIFY
|
|
select SOC_INTEL_UFS_OCP_TIMER_DISABLE
|
|
help
|
|
Selects the workarounds applicable for Alder Lake SoC.
|
|
|
|
config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
|
|
bool
|
|
help
|
|
Alder Lake SoC based OEM board design with UFS and non-UFS planned to use an
|
|
unified AP firmware which demanded to have a unified descriptor. It means UFS
|
|
controller needs to default fuse enabled to let UFS SKU to boot.
|
|
|
|
On such design with non-UFS SKU is exhibiting S0ix failure due to UFS remain
|
|
enabled in the strap although FSP-S is making the UFS controller function
|
|
disabled. The potential root cause of this behaviour is although the UFS
|
|
controller is function disabled but MPHY clock is still in active state.
|
|
|
|
A possible solution to this problem is to issue a warm reboot (if boot path is
|
|
S5->S0 or G3->S0) after disabling the UFS and let PMC to read the function
|
|
disable state of the UFS for disabling the MPHY clock.
|
|
|
|
Mainboard users with such board design where OEM would like to use an unified AP
|
|
firmware to support both UFS and non-UFS sku booting might need to choose this
|
|
config to allow disabling UFS while booting on the non-UFS SKU.
|
|
Note: selection of this config would introduce an additional warm reset in
|
|
cold-reset scenarios due to function disabling of the UFS controller.
|
|
|
|
if STITCH_ME_BIN
|
|
|
|
config CSE_BPDT_VERSION
|
|
default "1.7"
|
|
|
|
endif
|
|
|
|
config SI_DESC_REGION
|
|
string "Descriptor Region name"
|
|
default "SI_DESC"
|
|
help
|
|
Name of Descriptor Region in the FMAP
|
|
|
|
config SI_DESC_REGION_SZ
|
|
int
|
|
default 4096
|
|
help
|
|
Size of Descriptor Region in the FMAP
|
|
|
|
config BUILDING_WITH_DEBUG_FSP
|
|
bool "Debug FSP is used for the build"
|
|
default n
|
|
help
|
|
Set this option if debug build of FSP is used.
|
|
|
|
config INTEL_GMA_BCLV_OFFSET
|
|
default 0xc8258
|
|
|
|
config INTEL_GMA_BCLV_WIDTH
|
|
default 32
|
|
|
|
config INTEL_GMA_BCLM_OFFSET
|
|
default 0xc8254
|
|
|
|
config INTEL_GMA_BCLM_WIDTH
|
|
default 32
|
|
|
|
config FSP_PUBLISH_MBP_HOB
|
|
bool
|
|
default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N)
|
|
default y
|
|
help
|
|
This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
|
|
Disabling it for the platforms, which do not use MBP HOB, can improve the boot time.
|
|
|
|
Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on
|
|
MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't
|
|
occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the
|
|
later platforms so creation of MBP HOB can be skipped for ADL-N based platforms.
|
|
|
|
config INCLUDE_HSPHY_IN_FMAP
|
|
bool "Include PCIe 5.0 HSPHY firmware in flash"
|
|
default n
|
|
help
|
|
Set this option to cache the PCIe 5.0 HSPHY firmware after it is
|
|
fetched from ME during boot. By default coreboot will fetch the
|
|
HSPHY FW from ME, but if for some reason ME is not enabled or
|
|
visible, the cached blob will be attempted to initialize the PCIe
|
|
5.0 root port. Select it if ME is soft disabled or disabled with HAP
|
|
bit. If possible, the HSPHY FW will be saved to flashmap region if
|
|
the firmware file is not provided directly in the HSPHY_FW_FILE
|
|
Kconfig.
|
|
|
|
config HSPHY_FW_FILE
|
|
string "HSPHY firmware file path"
|
|
depends on INCLUDE_HSPHY_IN_FMAP
|
|
help
|
|
Path pointing to the PCIe 5.0 HSPHY file. The file can be extracted
|
|
from full firmware image or ME region using UEFITool. If left empty,
|
|
HSPHY loading procedure will try to save the firmware to the flashmap
|
|
region if fetched successfully from ME.
|
|
|
|
config HSPHY_FW_MAX_SIZE
|
|
hex
|
|
default 0x8000
|
|
|
|
config HAVE_BMP_LOGO_COMPRESS_LZMA
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
|
|
default 0x2005
|
|
help
|
|
slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz).
|
|
|
|
endif
|