system76-coreboot

Files

Furquan Shaikh c681409a8a soc/intel/apollolake: Correct PCI write size in romstage

1. PCI command reg write should be 16-bit.
2. HPTC reg write should be 8-bit. Also, use macros instead of
hard-coded values. Currently, the macros are defined in romstage.c,
but if more P2SB macros are added, it would be good to move them to a
separate header file.

Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14613
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>

2016-05-06 06:52:28 +02:00

acpi

acpi/: add missing license header

2016-01-14 22:52:11 +01:00

arch

arch/x86: Drop CBFS_BASE_ADDRESS

2016-05-03 11:41:55 +02:00

commonlib

ensure correct byte ordering for cbfs segment list

2016-04-25 23:30:00 +02:00

console

arch/x86: introduce postcar stage/phase