c6a106286b
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <reset.h>
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFFF) << 20) | \
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(((DEV) & 0x1F) << 15) | \
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(((FN) & 0x7) << 12))
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typedef unsigned device_t;
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static void pci_write_config32(device_t dev, unsigned where, unsigned value)
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{
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unsigned addr;
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addr = (dev>>4) | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(value, 0xCFC);
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}
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static unsigned pci_read_config32(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = (dev>>4) | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inl(0xCFC);
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}
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#include "../../../northbridge/amd/amdk8/reset_test.c"
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void hard_reset(void)
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{
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set_bios_reset();
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/* Try rebooting through port 0xcf9 */
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/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
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outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
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outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
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}
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