4c3ab7376e
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
130 lines
3.6 KiB
C
130 lines
3.6 KiB
C
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/* cpuRegInit */
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void cpuRegInit (void)
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{
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int msrnum;
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msr_t msr;
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/* The following is only for diagnostics mode; do not use for OLPC */
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if (0) {
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/* Set Diagnostic Mode */
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msrnum = CPU_GLD_MSR_DIAG;
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msr.hi = 0;
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msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
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wrmsr(msrnum, msr);
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/* Set up GLCP to grab BTM data. */
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msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */
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msr.hi = 0x0;
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msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */
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/* Turn off debug clock */
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msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */
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msr.lo = 0x00; /* No clock */
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* Set debug clock to CPU */
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msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */
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msr.lo = 0x01; /* CPU CLOCK */
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* Set fifo ctl to BTM bits wide */
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msrnum = GLCP_FIFOCTL; /* FIFO_CTL */
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msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */
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wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */
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/* Bit [19] sets it up in slow data mode. */
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/* enable fifo loading - BTM sizing will constrain */
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/* only valid BTM packets to load - this action should always be on */
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msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo */
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msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger */
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* start storing diag data in the fifo */
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msrnum = 0x04C00005F; /* DIAG CTL */
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msr.lo = 0x080000000; /* enable actions */
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* Set up delay on data lines, so that the hold time */
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/* is 1 ns. */
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msrnum = GLCP_PROCSTAT; /* GLCP IO DELAY CONTROLS */
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msr.lo = 0x082b5ad68;
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msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */
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wrmsr(msrnum, msr);
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/* Set up DF to output diag information on DF pins. */
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msrnum = DF_GLD_MSR_MASTER_CONF;
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msr.lo = 0x0220;
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msr.hi = 0;
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wrmsr(msrnum, msr);
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msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */
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msr.hi = 0x0;
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msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
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wrmsr(msrnum, msr);
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/* end of code for BTM */
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}
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/* Enable Suspend on Halt */
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msrnum = CPU_XC_CONFIG;
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msr = rdmsr(msrnum);
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msr.lo |= XC_CONFIG_SUSP_ON_HLT;
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wrmsr(msrnum, msr);
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/* ENable SUSP and allow TSC to run in Suspend */
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/* to keep speed detection happy */
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msrnum = CPU_BC_CONF_0;
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msr = rdmsr(msrnum);
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msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
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wrmsr(msrnum, msr);
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/* Setup throttling to proper mode if it is ever enabled. */
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msrnum = GLCP_TH_OD;
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msr.hi = 0x000000000;
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msr.lo = 0x00000603C;
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wrmsr(msrnum, msr);
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/* FooGlue Setup */
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/* Set CS5535/CS5536 mode in FooGlue */
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msrnum = FG_GIO_MSR_SEL;
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msr = rdmsr(msrnum);
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msr.lo &= ~3;
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msr.lo |= 2; /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */
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wrmsr(msrnum, msr);
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/* Disable DOT PLL. Graphics init will enable it if needed. */
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msrnum = GLCP_DOTPLL;
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msr = rdmsr(msrnum);
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msr.lo |= DOTPPL_LOWER_PD_SET;
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wrmsr(msrnum, msr);
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/* Enable RSDC */
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msrnum = CPU_AC_SMM_CTL;
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msr = rdmsr(msrnum);
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msr.lo |= 0x08;
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wrmsr(msrnum, msr);
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/* Enable BTB */
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/* I hate to put this check here but it doesn't really work in cpubug.asm */
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msrnum = GLCP_CHIP_REVID;
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msr = rdmsr(msrnum);
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if (msr.lo >= CPU_REV_2_1){
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msrnum = CPU_PF_BTB_CONF;
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msr = rdmsr(msrnum);
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msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
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wrmsr(msrnum, msr);
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}
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/* FPU imprecise exceptions bit */
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{
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msrnum = CPU_FPU_MSR_MODE;
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msr = rdmsr(msrnum);
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msr.lo |= FPU_IE_SET;
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wrmsr(msrnum, msr);
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}
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}
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