c700829cd3
These were OEM configurations hidden inside a header file, notation was already dropped for f15tb and f16kb. Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled,
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ChannelTypeExt6db,
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4,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1,
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46)
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},
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/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled,
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ChannelTypeExt6db,
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5,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1,
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46)
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},
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/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled,
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ChannelTypeExt6db,
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6,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1,
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46)
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},
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/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
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PCIE_PORT_DATA_INITIALIZER(PortDisabled,
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ChannelTypeExt6db,
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7,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1,
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0)
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},
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/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled,
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ChannelTypeExt6db,
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8,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1,
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0)
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}
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* (DDI interface Lanes 8:11, DdA, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
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{ConnectorTypeLvds, Aux1, Hdp1}
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},
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/* (DDI interface Lanes 12:15, DdB, ...) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
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/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
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{ConnectorTypeDP, Aux2, Hdp2}
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}
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList,
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};
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->GnbConfig.PsppPolicy = 0;
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}
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/**
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* @brief Customer Overides Memory Table
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*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform
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* information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...).
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* If PlatformSpecificTable is populated, AGESA will base its settings on the
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* data from the table. Otherwise, it will use its default conservative settings.
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*/
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static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
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PSO_END
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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