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c72df501a1f04df8ea6b03b97b7ddd0882c9ba19
system76-coreboot/src
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Ronak Kanabar c72df501a1 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01 
The headers added are generated as per FSP v2265_01.
Previous FSP version was v2237_00.
Changes Include:
- Add Irms UPD in FspsUpd.h
- Adjust Reserved UPD Offset in FspsUpd.h
- Few UPDs description update in FspmUpd.h

BUG=b:194032028
BRANCH=None
TEST=Build and boot brya

Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f
Cq-Depend:chrome-internal:4004482
Cq-Depend:chrome-internal:4003608
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30 17:32:49 +00:00
..
acpi
acpi: Add function to simplify If (CondRefOf (..)) sequences
2021-07-12 07:34:44 +00:00
arch
arch/x86/thread: Add #error when compiling for x86_64
2021-07-29 09:12:24 +00:00
commonlib
commonlib: Add timestamp strings for TS_FSP_MULTI_PHASE_SI_INIT_x
2021-07-29 09:10:45 +00:00
console
Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80s
2021-06-25 15:51:20 +00:00
cpu
cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPI
2021-07-27 14:00:32 +00:00
device
device/pci_rom: Make ON_DEVICE_ROM_LOAD condition truthy
2021-07-20 16:52:35 +00:00
drivers
src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
2021-07-24 15:18:43 +00:00
ec
ec/roda/it8518/acpi: Remove unnecessary assignments
2021-07-28 13:50:59 +00:00
include
include/acpi/acpi.h: add comment about raw data in generic error status
2021-07-27 22:45:52 +00:00
lib
arch/x86,lib/thread: Enable thread support in romstage
2021-07-26 07:30:48 +00:00
mainboard
mb/google/brya/variants/primus: Disable PCIe6
2021-07-30 05:08:53 +00:00
northbridge
src/*: Specify type of CBFS_SIZE once
2021-07-26 14:02:57 +00:00
security
vboot/secdata_tpm: Add WRITE_STCLEAR attr to RW ARB spaces
2021-07-26 07:27:48 +00:00
soc
soc/intel/elkhartlake: Update UART clock divider params
2021-07-29 05:18:48 +00:00
southbridge
soc/amd/common/block/acpimmio: add Kconfig option for biosram accessors
2021-07-26 19:34:20 +00:00
superio
src: Retype option API to use unsigned integers
2021-05-06 14:48:15 +00:00
vendorcode
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01
2021-07-30 17:32:49 +00:00
Kconfig
option: Allow mainboards to implement the API
2021-05-28 11:37:25 +00:00