ce22c02387
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
91 lines
2.0 KiB
C
91 lines
2.0 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MIPS_ARCH_EXCEPTION_H__
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#define __MIPS_ARCH_EXCEPTION_H__
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#include <stdint.h>
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void exception_init_asm(void);
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void exception_dispatch(void);
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struct exception_state_t {
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struct {
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/* Always 0: just to keep the series complete */
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u32 zero;
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/* Reserved for the assembler */
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/* TODO: is this actually needed here? */
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u32 at;
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/* v0-v1: expression evaluation */
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u32 v0;
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u32 v1;
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/* a0-a3: Arguments */
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u32 a0;
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u32 a1;
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u32 a2;
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u32 a3;
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/* t0-t3: Temporary registers for expression evaluation */
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u32 t0;
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u32 t1;
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u32 t2;
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u32 t3;
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u32 t4;
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u32 t5;
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u32 t6;
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u32 t7;
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/* s0-s7: Saved registers */
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u32 s0;
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u32 s1;
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u32 s2;
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u32 s3;
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u32 s4;
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u32 s5;
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u32 s6;
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u32 s7;
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/* t8-t9: Temporary registers for expression evaluation */
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u32 t8;
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u32 t9;
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/* k0-k1: reserved for SO kernel */
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u32 k0;
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u32 k1;
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/* Global pointer */
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u32 gp;
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/* Stack pointer */
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u32 sp;
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/* Frame pointer */
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u32 fp;
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/* Return address */
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u32 ra;
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} regs;
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u32 vector;
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} __attribute__((packed));
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extern struct exception_state_t *exception_state_ptr;
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extern u32 *exception_stack_end;
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enum {
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EXC_CACHE_ERROR = 0,
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EXC_TLB_REFILL_AND_ALL = 1,
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EXC_INTERRUPT = 2,
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EXC_EJTAG_DEBUG = 3,
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EXC_COUNT
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};
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#endif /* __MIPS_ARCH_EXCEPTION_H__ */
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