c86c6b33e8
Having same memory region set as both WRPROT and WRBACK using MTRRs is undefined behaviour. This could happen if we allow DCACHE_RAM_BASE to be located within CBFS in SPI flash memory and XIP romstage is at the same location. As SPI master by default decodes all of top 16MiB below 4GiB, initial cache-as-ram line fills may have actually read from SPI flash even in the case DCACHE_RAM_BASE was below the nominal 4GiB - ROM_SIZE. There are no reasons to have this as board-specific setting. Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
19 lines
243 B
Plaintext
19 lines
243 B
Plaintext
config CPU_INTEL_SOCKET_LGA771
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bool
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select CPU_INTEL_MODEL_6FX
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select SSE2
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select MMX
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select AP_IN_SIPI_WAIT
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if CPU_INTEL_SOCKET_LGA771
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config DCACHE_RAM_BASE
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hex
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default 0xfefc0000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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endif
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