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of the ugly mixture it was before. It also enables CAR for all C7 boards Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
60 lines
1.2 KiB
Plaintext
60 lines
1.2 KiB
Plaintext
source src/cpu/amd/Kconfig
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source src/cpu/intel/Kconfig
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source src/cpu/via/Kconfig
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source src/cpu/x86/Kconfig
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config USE_DCACHE_RAM
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bool
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default !ROMCC
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config DCACHE_RAM_BASE
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hex
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config DCACHE_RAM_SIZE
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hex
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x0
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config SMP
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bool
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default y if MAX_CPUS != 1
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default n
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help
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor (SMP) systems.
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config MMX
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bool
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help
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Select MMX in your socket or model Kconfig if your CPU has MMX
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to MMX registers.
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config SSE
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bool
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help
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Select SSE in your socket or model Kconfig if your CPU has SSE
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to SSE (aka XMM) registers.
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config SSE2
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bool
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default n
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help
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Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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streaming SIMD instructions. Some parts of coreboot can be built
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with more efficient code if SSE2 instructions are available.
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config VAR_MTRR_HOLE
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bool
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default y
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help
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Unset this if you don't want the MTRR code to use
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subtractive MTRRs
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