c8eab2c044
The patch is based on Thatcher board. So far it boots Linux (3.2/3.7), internal network adapter works, AHCI works. External PCI/PCIe slots works too. Power management/ACPI seems to work. Internal VGA works with dumped ROM (VGA/DVI), but lacks GART. PCI pref devices are being relocated by Linux, reason unknown. This is a good start. USB and XHCI untested but visible. Change-Id: I1869aecb2634d548b00b3c9139517d6a0e0c9817 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/2038 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include "BiosCallOuts.h"
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <arch/acpi.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include "agesawrapper.h"
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/*************************************************
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* enable the dedicated function in thatcher board.
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*************************************************/
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static void mainboard_enable(device_t dev)
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{
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msr_t msr;
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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msr = rdmsr(0xC0011020);
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msr.lo &= ~(1 << 28);
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wrmsr(0xC0011020, msr);
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msr = rdmsr(0xC0011022);
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msr.lo &= ~(1 << 4);
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msr.lo &= ~(1 << 13);
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wrmsr(0xC0011022, msr);
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msr = rdmsr(0xC0011023);
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msr.lo &= ~(1 << 23);
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wrmsr(0xC0011023, msr);
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/*
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* The mainboard is the first place that we get control in ramstage. Check
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* for S3 resume and call the approriate AGESA/CIMx resume functions.
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*/
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#if CONFIG_HAVE_ACPI_RESUME
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acpi_slp_type = acpi_get_sleep_type();
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if (acpi_slp_type == 3)
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agesawrapper_fchs3earlyrestore();
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#endif
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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