Felix Held 455d7b74ab soc/amd/picasso/tsc: fix clock divisor range check
The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.

TEST=Compared with Picasso's PPR #55570

Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05 09:44:23 +00:00
..
2020-12-02 23:35:58 +00:00
2020-12-02 23:35:58 +00:00