c97802fd4a
This makes it easier to spot differences. Change-Id: I16596a661ee4e56c2cb1d0aef663067ae6159705 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
105 lines
3.5 KiB
Plaintext
105 lines
3.5 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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# Copyright (C) 2018 Robert Reeves
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/sandybridge
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device cpu_cluster 0x0 on
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0x0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0x0 on
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subsystemid 0x103c 0x176c inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on # PCIe Bridge for discrete graphics
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device pci 00.0 on end # GPU
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device pci 00.1 on end # HDMI Audio on GPU
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end
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device pci 02.0 off end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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# mailbox at 0x200/0x201 and PM1 at 0x220
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register "gen1_dec" = "0x007c0201"
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register "gen2_dec" = "0x000c0101"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x1f"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # HD Audio controller
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2
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device pci 1c.2 on end # Media Card and FireWire host controller
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device pci 1c.3 on end # Wireless LAN Adapter
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device pci 1c.4 on end # SATA Controller 2 for dock
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x62"
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register "ec_cmd_port" = "0x66"
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register "ec_ctrl_reg" = "0x81"
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register "ec_fan_ctrl_value" = "0x81"
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device pnp ff.1 off end
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end
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chip superio/smsc/lpc47n217
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device pnp 4e.3 on # Parallel
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 4e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.5 off end # COM2
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 off end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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end
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end
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