c9871505f1
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is confusing. Previously the region was shared for heap and stack, starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs. Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of stack guards and reduces amount of reserved CAR for bootblock and verstage, as the new allocation in .bss is only taken in romstage. BUG=b:140268415 Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
216 lines
6.1 KiB
Plaintext
216 lines
6.1 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015-2018 Intel Corp.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config PLATFORM_USES_FSP2_0
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bool
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default n
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help
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Include FSP 2.0 wrappers and functionality
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config PLATFORM_USES_FSP2_1
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bool
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default n
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select PLATFORM_USES_FSP2_0
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select FSP_USES_CB_STACK
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select FSP_PEIM_TO_PEIM_INTERFACE
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help
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Include FSP 2.1 wrappers and functionality.
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Features added into FSP 2.1 specification that impacts coreboot are:
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1. Remove FSP stack switch and use the same stack with boot firmware
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2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE
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if PLATFORM_USES_FSP2_0
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config ADD_FSP_BINARIES
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bool "Add Intel FSP 2.0 binaries to CBFS"
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help
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Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
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use the FSP-T binary and it is not added.
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config DISPLAY_FSP_CALLS_AND_STATUS
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bool "Display the FSP calls and status"
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default n
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help
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Display the FSP call entry point and parameters prior to calling FSP
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and display the status upon return from FSP.
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config DISPLAY_FSP_HEADER
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bool "Display the FSP header"
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default n
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help
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Display the FSP header information when the FSP file is found.
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config DISPLAY_HOBS
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bool "Display the hand-off-blocks"
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default n
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help
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Display the FSP HOBs which are provided for coreboot.
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config DISPLAY_UPD_DATA
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bool "Display UPD data"
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default n
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help
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Display the user specified product data prior to memory
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initialization.
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config CPU_MICROCODE_CBFS_LEN
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hex "Microcode update region length in bytes"
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depends on FSP_CAR
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default 0x0
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help
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The length in bytes of the microcode update region.
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config CPU_MICROCODE_CBFS_LOC
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hex "Microcode update base address in CBFS"
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depends on FSP_CAR
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default 0x0
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help
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The location (base address) in CBFS that contains the
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microcode update binary.
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config FSP_T_CBFS
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string "Name of FSP-T in CBFS"
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depends on FSP_CAR
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default "fspt.bin"
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config FSP_S_CBFS
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string "Name of FSP-S in CBFS"
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default "fsps.bin"
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config FSP_M_CBFS
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string "Name of FSP-M in CBFS"
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default "fspm.bin"
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config FSP_USE_REPO
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bool "Use the IntelFSP based binaries"
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depends on ADD_FSP_BINARIES
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depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
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SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
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SOC_INTEL_WHISKEYLAKE
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help
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When selecting this option, the SoC must set FSP_HEADER_PATH
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and FSP_FD_PATH correctly so FSP splitting works.
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config FSP_T_FILE
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string "Intel FSP-T (temp ram init) binary path and filename"
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depends on FSP_CAR
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default "$(obj)/Fsp_T.fd" if FSP_USE_REPO
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help
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The path and filename of the Intel FSP-M binary for this platform.
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config FSP_M_FILE
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string "Intel FSP-M (memory init) binary path and filename"
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depends on ADD_FSP_BINARIES
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default "$(obj)/Fsp_M.fd" if FSP_USE_REPO
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help
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The path and filename of the Intel FSP-M binary for this platform.
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config FSP_S_FILE
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string "Intel FSP-S (silicon init) binary path and filename"
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depends on ADD_FSP_BINARIES
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default "$(obj)/Fsp_S.fd" if FSP_USE_REPO
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help
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The path and filename of the Intel FSP-S binary for this platform.
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config FSP_CAR
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bool "Use FSP TempRamInit & TempRamExit APIs"
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depends on ADD_FSP_BINARIES
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default n
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help
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Use FSP APIs to initialize & Tear Down the Cache-As-Ram
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config FSP_M_XIP
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bool "Is FSP-M XIP"
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default n
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help
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Select this value when FSP-M is execute-in-place.
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config FSP_T_XIP
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bool
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default n
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help
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Select this value when FSP-T is execute-in-place.
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config FSP_USES_CB_STACK
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bool
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default n
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help
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Enable support for fsp to use same stack as coreboot.
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This option allows fsp to continue using coreboot stack
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without reinitializing stack pointer. This feature is
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supported Icelake onwards.
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x10000
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depends on FSP_USES_CB_STACK
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config VERIFY_HOBS
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bool "Verify the FSP hand-off-blocks"
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default n
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help
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Verify that the HOBs required by coreboot are returned by FSP and
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that the resource HOBs are in the correct order and position.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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config DISPLAY_FSP_VERSION_INFO
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bool "Display Firmware Ingredient Version Information"
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help
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Select this option to display Firmware version information.
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config FSP2_0_USES_TPM_MRC_HASH
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bool
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depends on TPM1 || TPM2
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depends on VBOOT && VBOOT_STARTS_IN_BOOTBLOCK
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default y if HAS_RECOVERY_MRC_CACHE
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default n
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select VBOOT_HAS_REC_HASH_SPACE
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help
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Store hash of trained recovery MRC cache in NVRAM space in TPM.
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Use the hash to validate recovery MRC cache before using it.
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This hash needs to be updated every time recovery mode training
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is recomputed, or if the hash does not match recovery MRC cache.
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Selecting this option requires that TPM already be setup by this
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point in time. Thus it is only compatible when the option
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VBOOT_STARTS_IN_BOOTBLOCK is selected, which causes verstage and
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TPM setup to occur prior to memory initialization.
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config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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bool
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help
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This is selected by SoC or mainboard to supply their own
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concept of a version for the memory settings respectively.
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This allows deployed systems to bump their version number
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with the same FSP which will trigger a retrain of the memory.
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config FSP_PEIM_TO_PEIM_INTERFACE
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bool
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select FSP_USES_MP_SERVICES_PPI
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help
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This option allows SOC user to create specific PPI for Intel FSP
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usage, coreboot will provide required PPI structure definitions
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along with all APIs as per EFI specification. So far this feature
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is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
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useful to add further PPI if required.
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if FSP_PEIM_TO_PEIM_INTERFACE
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source "src/drivers/intel/fsp2_0/ppi/Kconfig"
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endif
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endif
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