ca87532a07
AGESA sets up MTRRs so these functions are now unused. Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
76 lines
1.9 KiB
C
76 lines
1.9 KiB
C
#ifndef CPU_AMD_MTRR_H
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#define CPU_AMD_MTRR_H
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#define MTRR_IORR0_BASE 0xC0010016
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#define MTRR_IORR0_MASK 0xC0010017
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#define MTRR_IORR1_BASE 0xC0010018
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#define MTRR_IORR1_MASK 0xC0010019
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#define MTRR_READ_MEM (1 << 4)
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#define MTRR_WRITE_MEM (1 << 3)
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#define SYSCFG_MSR 0xC0010010
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#define SYSCFG_MSR_TOM2WB (1 << 22)
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#define SYSCFG_MSR_TOM2En (1 << 21)
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#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
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#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
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#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
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#define SYSCFG_MSR_UcLockEn (1 << 17)
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#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
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#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
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#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
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#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
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#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
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#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
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#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
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#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
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#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
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#if defined(__ASSEMBLER__)
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#define TOP_MEM 0xC001001A
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#define TOP_MEM2 0xC001001D
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#else
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#define TOP_MEM 0xC001001Aul
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#define TOP_MEM2 0xC001001Dul
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#endif
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#define TOP_MEM_MASK 0x007fffff
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#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
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#if !defined(__ASSEMBLER__)
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#include <cpu/x86/msr.h>
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#include <stdint.h>
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struct device;
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void add_uma_resource_below_tolm(struct device *nb, int idx);
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static __always_inline msr_t rdmsr_amd(unsigned int index)
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{
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msr_t result;
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__asm__ __volatile__ (
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"rdmsr"
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: "=a" (result.lo), "=d" (result.hi)
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: "c"(index), "D"(0x9c5a203a)
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);
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return result;
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}
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static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
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{
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__asm__ __volatile__ (
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"wrmsr"
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: /* No outputs */
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: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
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);
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}
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/* To distribute topmem MSRs to APs. */
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void setup_bsp_ramtop(void);
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uint64_t bsp_topmem(void);
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uint64_t bsp_topmem2(void);
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#endif
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#endif /* CPU_AMD_MTRR_H */
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