cab9efb2be
Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/6147 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
324 lines
8.3 KiB
C
324 lines
8.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <delay.h>
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#include "rs690.h"
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static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
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{
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pci_write_config32(dev, index_reg, index);
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return pci_read_config32(dev, index_reg + 0x4);
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}
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static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
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{
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pci_write_config32(dev, index_reg, index);
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pci_write_config32(dev, index_reg + 0x4, data);
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}
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/* extension registers */
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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{
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.pci.devfn);
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addr |= dev->bus->secondary << 20 | /* bus num */
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dev->path.pci.devfn << 12 | reg;
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return *((u32 *) addr);
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}
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void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
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dev->path.pci.devfn);*/
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addr |= dev->bus->secondary << 20 | /* bus num */
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dev->path.pci.devfn << 12 | reg_pos;
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reg = reg_old = *((u32 *) addr);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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*((u32 *) addr) = reg;
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}
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}
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u32 nbmisc_read_index(device_t nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBMISC_INDEX, (index));
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}
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void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
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}
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u32 nbpcie_p_read_index(device_t dev, u32 index)
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{
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return nb_read_index((dev), NBPCIE_INDEX, (index));
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}
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void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
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{
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nb_write_index((dev), NBPCIE_INDEX, (index), (data));
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}
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u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
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}
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void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
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}
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u32 htiu_read_index(device_t nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
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}
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void htiu_write_index(device_t nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
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}
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u32 nbmc_read_index(device_t nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBMC_INDEX, (index));
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}
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void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
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}
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void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = pci_read_config32(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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pci_write_config32(nb_dev, reg_pos, reg);
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}
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}
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void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
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{
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u8 reg_old, reg;
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reg = reg_old = pci_read_config8(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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pci_write_config8(nb_dev, reg_pos, reg);
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}
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}
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void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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nbmc_write_index(nb_dev, reg_pos, reg);
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}
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}
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void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = htiu_read_index(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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htiu_write_index(nb_dev, reg_pos, reg);
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}
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}
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void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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nbmisc_write_index(nb_dev, reg_pos, reg);
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}
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}
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void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
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}
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}
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/*
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* To access bar3 we need to program PCI MMIO 7 in K8.
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* in_out:
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* 1: enable/enter k8 temp mmio base
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* 0: disable/restore
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*/
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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{
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/* K8 Function1 is address map */
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device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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if (in_out) {
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u32 dword, sblk;
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/* Get SBLink value (HyperTransport I/O Hub Link ID). */
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dword = pci_read_config32(k8_f0, 0x64);
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sblk = (dword >> 8) & 0x3;
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/* Fill MMIO limit/base pair. */
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pci_write_config32(k8_f1, 0xbc,
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(((pcie_base_add + 0x10000000 -
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1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
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pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
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pci_write_config32(k8_f1, 0xb4,
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(((mmio_base_add + 0x10000000 -
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1) >> 8) & 0xffffff00) | (sblk << 4));
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pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
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} else {
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pci_write_config32(k8_f1, 0xb8, 0);
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pci_write_config32(k8_f1, 0xbc, 0);
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pci_write_config32(k8_f1, 0xb0, 0);
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pci_write_config32(k8_f1, 0xb4, 0);
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}
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}
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void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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{
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switch (port) {
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case 2: /* GFX, bit4-5 */
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case 3:
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set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
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1 << (port + 2), 0 << (port + 2));
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break;
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case 4: /* GPP, bit20-24 */
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case 5:
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case 6:
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case 7:
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set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
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1 << (port + 17), 0 << (port + 17));
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break;
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}
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}
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/*
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* Output:
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* 0: no device is present.
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* 1: device is present and is trained.
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*/
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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{
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u16 count = 5000;
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u32 lc_state, reg;
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int8_t current, res = 0;
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while (count--) {
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mdelay(40);
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udelay(200);
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lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */
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printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
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port, lc_state);
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current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
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switch (current) {
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case 0x00: /* 0x00-0x04 means no device is present */
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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res = 0;
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count = 0;
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break;
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case 0x07: /* device is in compliance state (training sequence is doen). Move to train the next device */
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res = 1; /* TODO: CIM sets it to 0 */
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count = 0;
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break;
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case 0x10:
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reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS);
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printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
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/* check bit1 */
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if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
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/* set bit8=1, bit0-2=bit4-6 */
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u32 tmp;
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reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
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tmp = (reg >> 4) & 0x07; /* get bit4-6 */
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reg &= 0xfff8; /* clear bit0-2 */
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reg += tmp; /* merge */
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reg |= 1 << 8;
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nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
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count++; /* CIM said "keep in loop"? */
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} else {
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res = 1;
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count = 0;
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}
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break;
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default: /* reset pcie */
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res = 0;
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count = 0; /* break loop */
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break;
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}
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}
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return res;
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}
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/*
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* Compliant with CIM_33's ATINB_SetToms.
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* Set Top Of Memory below and above 4G.
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*/
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void rs690_set_tom(device_t nb_dev)
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{
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/* set TOM */
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#if CONFIG_GFXUMA
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pci_write_config32(nb_dev, 0x90, uma_memory_base);
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nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
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#else
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/* 1GB system memory supposed */
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pci_write_config32(nb_dev, 0x90, 0x38000000);
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nbmc_write_index(nb_dev, 0x1e, 0x38000000);
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#endif
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}
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