cb3f498296
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
143 lines
2.9 KiB
C
143 lines
2.9 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8601/raminit.h"
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/*
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*/
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void udelay(int usecs) {
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "debug.c"
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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#define MAXIMUM_CONSOLE_LOGLEVEL 9
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#define DEFAULT_CONSOLE_LOGLEVEL 9
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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static void memreset_setup(void)
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{
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}
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/*
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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}
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#include "northbridge/via/vt8601/raminit.c"
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/*
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#include "sdram/generic_sdram.c"
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*/
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static void
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enable_mainboard_devices(void) {
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device_t dev;
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/* dev 0 for southbridge */
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dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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#if 0
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// This early setup switches IDE into compatibility mode before PCI gets
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// // a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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//
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#endif
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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*/
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dev++; /* ICKY */
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pci_write_config8(dev, 0x42, 0);
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}
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static void
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enable_shadow_ram(void) {
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static void main(void)
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{
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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enable_mainboard_devices();
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uart_init();
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console_init();
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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}
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